• Title/Summary/Keyword: Short Fault

검색결과 532건 처리시간 0.023초

Detection of Stator Winding Inter-Turn Short Circuit Faults in Permanent Magnet Synchronous Motors and Automatic Classification of Fault Severity via a Pattern Recognition System

  • CIRA, Ferhat;ARKAN, Muslum;GUMUS, Bilal
    • Journal of Electrical Engineering and Technology
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    • 제11권2호
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    • pp.416-424
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    • 2016
  • In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

Study on Application of Superconducting Fault Current Limiter Considering Risk of Circuit Breaker Short-Circuit Capacity in a Loop Network System

  • Kim, Jin-Seok;Lim, Sung-Hun;Kim, Jae-Chul
    • Journal of Electrical Engineering and Technology
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    • 제9권6호
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    • pp.1789-1794
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    • 2014
  • This paper suggests an application method for a superconducting fault current limiter (SFCL) using an evaluation index to estimate the risk regarding the short-circuit capacity of the circuit breaker (CB). Recently, power distribution systems have become more complex to ensure that supply continuously keeps pace with the growth of demand. However, the mesh or loop network power systems suffer from a problem in which the fault current exceeds the short-circuit capacity of the CBs when a fault occurs. Most case studies on the application of the SFCL have focused on its development and performance in limiting fault current. In this study, an analysis of the application method of an SFCL considering the risk of the CB's short-circuit capacitor was carried out in situations when a fault occurs in a loop network power system, where each line connected with the fault point carries a different current that is above or below the short-circuit capacitor of the CB. A loop network power system using PSCAD/EMTDC was modeled to investigate the risk ratio of the CB and the effect of the SFCL on the reduction of fault current through various case studies. Through the risk evaluations of the simulation results, the estimation of the risk ratio is adequate to apply the SFCL and demonstrate the fault current limiting effect.

Fault Detection 기능을 갖는 이오나이저 모듈용 게이트 구동 칩 설계 (Design of Gate Driver Chip for Ionizer Modules with Fault Detection Function)

  • 김홍주;하판봉;김영희
    • 전기전자학회논문지
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    • 제24권1호
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    • pp.132-139
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    • 2020
  • 공기청정기에 사용되는 이오나이저 모듈은 권선형 transformer를 사용하여 방전전극인 HV+/HV-에 3.5KV/-4KV의 고전압을 공급하여 carbon fiber brush의 전계 방사에 의해 양이온과 음이온을 발생시킨다. 기존의 MCU를 이용한 이오나이저 모듈 회로는 PCB 사이즈가 크고 가격이 비싼 단점이 있고, 기존의 ring oscillator를 이용한 게이트 구동 칩은 oscillation 주기가 PVT(Process-Voltage-Temperature) 변동에 민감하고 HV+와 GND, HV-와 GND의 단락에 의한 fault detection 기능이 없으므로 화재나 감전의 위험이 있다. 그래서 본 논문에서는 7bit binary UP counter를 이용하여 PVT 변동이 있더라도 oscillation 주기를 조절하여 HV+ 전압이 목표 전압에 도달하게 한다. 그리고 HV+와 GND 사이의 단락을 검출하기 위한 HV+ short fault detection 회로, HV-와 GND 사이의 단락을 검출하기 위한 HV- short fault detection 회로와 HV+가 과전압 이상으로 올라가는 것을 검출하기 위한 OVP(Over-Voltage Protection) 회로를 새롭게 제안하였다.

Investigation of Fault-Mode Behaviors of Matrix Converters

  • Kwak, Sang-Shin
    • Journal of Power Electronics
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    • 제9권6호
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    • pp.949-959
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    • 2009
  • This paper presents a systematic investigation of the fault-mode behaviors of matrix converter systems. Knowledge about converter behaviors after fault occurrence is important from the standpoint of reliable system design, protection and fault-tolerant control. Converter behaviors have been, in detail, examined with both qualitative and quantitative approaches for key fault types, such as switch open-circuited faults and switch short-circuited faults. Investigating the fault-mode behaviors of matrix converters reveals that converter operation with switch short-circuited faults leads to overvoltage stresses as well as overcurrent stresses on other healthy switching components. On the other hand, switch open-circuited faults only result in overvoltage to other switching components. This study can be used to predict fault-mode converter behaviors and determine additional stresses on remaining power circuit components under fault-mode operations.

IEC 60909에 의한 삼상 고장계산 (Three-phase Fault Calculation by IEC 60909)

  • 손석금
    • 전기학회논문지P
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    • 제63권1호
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    • pp.12-18
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    • 2014
  • This paper analyzes how to calculate the three phase short circuit current calculation procedures used in the IEC 60909 short circuit. It presented the new procedure of the fault current for the interrupting capacity of the circuit breaker. This procedure is applied to the future power system and calculates the fault current. Power demands are increased because of the growth of the economy for this reason, the fault current of the power system is largely increased and the fault current procedure for the proper interrupting capacity calculation of the existing or the new circuit breaker is essential. How to calculate the three phase short circuit current for ac electrical system and select the high voltage and low voltage circuit breaker based on IEC 60909 standards.

IGBT 인버터를 위한 향상된 단락회로 보호기법 (An Improved Short Circuit Protection Scheme for IGBT Inverters)

  • 서범석;현동석
    • 전력전자학회논문지
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    • 제3권4호
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    • pp.426-436
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    • 1998
  • Identification of fault current during the operation of a power semiconductor switch and activation of suitable remedial actions are important for reliable operation of power converters. A short circuit is a basic and severe fault situation in a circuit structure such as voltage source converters. This paper presents a new active protection circuit for fast and precise clamping and safe shutdown of fault currents of the IGBTs. This circuit allows operation of the IGBTs with a higher on-state gate voltage, which can thereby reduce the conduction loss in the device without compromising the short circuit protection characteristics. The operation of the circuit is studied under various conditions, considering variation of temperature, rising rate of fault current, gate voltage value, and protection circuit parameters. An evaluation of the operation of the circuit is made using IGBTs from different to confirm the effectiveness of the protection circuit.

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병행 2회선 송전선로의 선간단락시 고장점 표정의 개선에 관한 연구 (A Study on Advanced Fault Locating for Short Fault of a Double Circuit Transmission Line)

  • 박유영;박철원
    • 조명전기설비학회논문지
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    • 제30권1호
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    • pp.28-37
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    • 2016
  • Fault locating is an important element to minimize the damage of power system. The computation error of fault locator may occur by the influence of the DC offset component during phasor extraction. In order to minimize the bad effects of DC offset component, this paper presents an improved fault location algorithm based on a DC offset removal filter for short fault in a double circuit transmission line. We have modeled a 154kV double circuit transmission line by the ATP software to demonstrate the effectiveness of the proposed fault locating algorithm. The line to line short faults were simulated and then collected simulation data was used. It can be seen that the error rate of fault locating estimation by the proposed algorithm decreases than the error rate of fault locating estimation by conventional algorithm.

765kV 비연가 송전선로에서 상간단락고장 시어 거리계전 알고리즘 (A New Distance Relaying Algorithm for Phase-to-Phase Short Fault in 765kV Untransposed Transmission Lines)

  • 안용진;강상회
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 A
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    • pp.455-457
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    • 2004
  • An accurate digital distance relaying algorithm which is immune to reactance effect of the fault resistance and the load current for phase-to-phase short fault in 765kV untransposed transmission lines is proposed. The algorithm can estimate adaptively the impedance to a fault point independent of the fault resistance. To compensate the magnitude and phase of the apparent impedance, this algorithm uses the angle of an impedance deviation vector. The impedance correction algorithm for phase-to-phase short fault uses a voltage equation at fault point to compensate the fault current at fault point. A series of tests using EMTP output data in a 765kv untransposed transmission lines have proved the accuracy and effectiveness of the proposed algorithm.

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Load Flow Calculation and Short Circuit Faults Transients in Dispersed Generation Systems

  • Hosseini, Seyed Hossein;Shahnia, Farhad;Tizghadam, Saeed
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.800-804
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    • 2005
  • Load flow and short circuit fault transients of a power distribution system with wind turbines as dispersed generation units is presented. Usage of renewable energies such as wind is already a small part of total installed power system in medium and low voltage networks. In this paper, a radial power distribution system with wind turbines is simulated using DIgSILENT PowerFactory software for their influence on load flow and short circuit fault transients. Short fault occurring in dispersed generation systems causes some problems for the system and costumers such as fault level increase or the problems of sudden fluctuations in the current, voltage, power and torque of the double fed induction machine utilized in the wind turbines which have been studied and investigated.

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내장된 CMOS 연산증폭기의 테스트 방법 (Test Method of an Embedded CMOS OP-AMP)

  • 김강철;송근호;한석붕
    • 한국정보통신학회논문지
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    • 제7권1호
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    • pp.100-105
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    • 2003
  • 본 논문에서는 CMOS 연산증폭기에 존재하는 모든 단락고장(short fault)과 개방고장(open fault)을 효과적으로 검출할 수 있는 새로운 테스트 방식을 제안한다. 제안하는 테스트 방식은 단위이득 대역폭(unit gain bandwidth)보다 큰 주파수를 가치는 단일 정현파를 이용한다. 이 방식은 하나의 테스트 패턴으로 모든 대상고장을 검출할 수 있으므로 테스트 패턴 생성을 위한 알고리즘이 간단하다. 따라서 패턴 생성 시간이 짧고, 테스트 비용을 줄일 수 있는 장점을 가지고 있다. 제안한 테스트 방식을 검증하기 위하여 2단 연산 증폭기를 설계하였으며, HSPICE 모의실험을 통하여 대상 고장에 대하여 높은 고장검출율(fault coverage)을 얻었다.