• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.85-88
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• 2002

In this paper, the proposed watermark algorithm is based on energy distribution of the subband coefficients in the frequency domain and edge of the original image in the spacial domain. Out of these information, the KeyMap which decides the embedded position of watermark is produced. And then the binary watermark is embedded into the wavelet coefficient of LL3 subband using KeyMap and LFSR(Linear Feedback Shift Register).

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.1886-1902
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• 1989

In this paper we discuss the generating algorithm of Kumar code sequences which are based on generalized bent sequences for FH-CDMA. The code sequence generator was constructed for the shift register stages n=4 over GF (5). Finally we analyze the characteristics fo Hamming correlation between two code sequences and the time-frequency correlatins of the complete waveform with the sinusoidal chips as the elemental waveforms.

• The Magazine of the IEIE
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• v.11 no.2
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• pp.1-11
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• 1984

본 지 2월호에서 구술한 선형부호에 이어 이번호에서는 순회부호에 대해 기술하고자 한다. 선형블럭부호중 중요한 부류에 속하는 순회부호(cyclic code)는 그 내용이 대수적 구조를 갖고 있어 부호화 회로는 물론 부호에 필요한 오증(syndrome)계산회로 등 귀환연결이 있는 치환레지스터(shift register)를 사용한 장치화(implementation)가 매우 용이하다는 이점이 있다. 이런 순회부호는 산발오진(random error)뿐 아니라 연집오진(burst error)도 정정할 수 있는 매우 효과적인 부호로서 다중오진정정능력(multiple error correcting capability)을 갖는 BCH부호도 순회부호의 일종이다.

• Review of KIISC
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• v.2 no.2
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• pp.64-80
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• 1992

전화망을 통과하는 음성신호에 대하여, 실시간에 공개열쇠방식의 암호화/복호화를 하기 위한 반도체 IC제조공정평가를 실시하였다. 초당 64k bit의 정보에 대하여 256 bit이상의 key를 갖는 RSA 방식 암호화를 위하여 modular multiplication 환경과 redundant number system을 채택하여 algori-multiple input shift register 를 사용하는 회로로 충족시키는 과정에서, 1.0 $이하의 CMOS공정이 요구된다는 결론에 도달하였으며, 이들 회로의 타당성은 저속 RSA chip의 분석 결과와 비교하여 확인하였다.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.832-835
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• 2004

In this paper, we proposed a blind watermarking algorithm to use characteristics of a scalar quantizer which is similar with the recommended in the JPEG2000 and JPEG. This algorithm shifts a quantization index according to the value of each watermark bit to prevent losing the watermark information during the compression by quantization. Therefore, the watermark is embedded during the process of quantization, not an additional process for watermarking, and adaptively applied as an assigned quantizer according to application area. In the embedding process, a LFSR(Linear feedback shift register) is used to hide the watermarking positions. Therefore the embedded watermark can be extracted by only the owner who knows the initial value of LFSR without the original image. The experimental results showed that the proposed algorithm satisfies the robustness and imperceptibility corresponding to the major requirement of watermarking.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.282-284
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• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.1-8
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• 2005

In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.544-551
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• 2015

In this paper, the design and implementation results of the optical flow estimator (OFE) for moving object detection (MOD) in advanced driver assistance system (ADAS). In the proposed design, Brox's algorithm with global optimization is considered, which shows the high performance in the vehicle environment. In addition, Cholesky factorization is applied to solve Euler-Lagrange equation in Brox's algorithm. Also, shift register bank is incorporated to reduce memory access rate. The proposed optical flow estimator was designed with Verilog-HDL, and FPGA board was used for the real-time verification. Implementation results show that the proposed optical flow estimator includes the logic slices of 40.4K, 155 DSP48s, and block memory of 11,290Kbits.

• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.