• Title/Summary/Keyword: Shift Register

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On algorithm for finding primitive polynomials over GF(q) (GF(q)상의 원시다항식 생성에 관한 연구)

  • 최희봉;원동호
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.35-42
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    • 2001
  • The primitive polynomial on GF(q) is used in the area of the scrambler, the error correcting code and decode, the random generator and the cipher, etc. The algorithm that generates efficiently the primitive polynomial on GF(q) was proposed by A.D. Porto. The algorithm is a method that generates the sequence of the primitive polynomial by repeating to find another primitive polynomial with a known primitive polynomial. In this paper, we propose the algorithm that is improved in the A.D. Porto algorithm. The running rime of the A.D. Porto a1gorithm is O($\textrm{km}^2$), the running time of the improved algorithm is 0(m(m+k)). Here, k is gcd(k, $q^m$-1). When we find the primitive polynomial with m odor, it is efficient that we use the improved algorithm in the condition k, m>>1.

Selectively Partial Encryption of Images in Wavelet Domain (웨이블릿 영역에서의 선택적 부분 영상 암호화)

  • ;Dujit Dey
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.6C
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    • pp.648-658
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    • 2003
  • As the usage of image/video contents increase, a security problem for the payed image data or the ones requiring confidentiality is raised. This paper proposed an image encryption methodology to hide the image information. The target data of it is the result from quantization in wavelet domain. This method encrypts only part of the image data rather than the whole data of the original image, in which three types of data selection methodologies were involved. First, by using the fact that the wavelet transform decomposes the original image into frequency sub-bands, only some of the frequency sub-bands were included in encryption to make the resulting image unrecognizable. In the data to represent each pixel, only MSBs were taken for encryption. Finally, pixels to be encrypted in a specific sub-band were selected randomly by using LFSR(Linear Feedback Shift Register). Part of the key for encryption was used for the seed value of LFSR and in selecting the parallel output bits of the LFSR for random selection so that the strength of encryption algorithm increased. The experiments have been performed with the proposed methods implemented in software for about 500 images, from which the result showed that only about 1/1000 amount of data to the original image can obtain the encryption effect not to recognize the original image. Consequently, we are sure that the proposed are efficient image encryption methods to acquire the high encryption effect with small amount of encryption. Also, in this paper, several encryption scheme according to the selection of the sub-bands and the number of bits from LFSR outputs for pixel selection have been proposed, and it has been shown that there exits a relation of trade-off between the execution time and the effect of the encryption. It means that the proposed methods can be selectively used according to the application areas. Also, because the proposed methods are performed in the application layer, they are expected to be a good solution for the end-to-end security problem, which is appearing as one of the important problems in the networks with both wired and wireless sections.

Implementation of a Predictor for Cell Phase Monitoring at the OLT in the ATM-PON (ATM-PON의 OLT에서 상향 셀 위상감시를 위한 예측기의 구현)

  • Mun, Sang-Cheol;Chung, Hae;Kim, Woon-Ha
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.2C
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    • pp.160-169
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    • 2002
  • An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.

Fast-Transient Digital LDO Regulator With Binary-Weighted Current Control (이진 가중치 전류 제어 기법을 이용한 고속 응답 디지털 LDO 레귤레이터)

  • Woo, Ki-Chan;Sim, Jae-Hyeon;Kim, Tae-Woo;Hwang, Seon-Kwang;Yang, Byung-Do
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.6
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    • pp.1154-1162
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    • 2016
  • This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

An Efficient Test Compression Scheme based on LFSR Reseeding (효율적인 LFSR 리시딩 기반의 테스트 압축 기법)

  • Kim, Hong-Sik;Kim, Hyun-Jin;Ahn, Jin-Ho;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.3
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    • pp.26-31
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    • 2009
  • A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

Hardware Design of High-Performance SAO in HEVC Encoder for Ultra HD Video Processing in Real Time (UHD 영상의 실시간 처리를 위한 고성능 HEVC SAO 부호화기 하드웨어 설계)

  • Cho, Hyun-pyo;Park, Seung-yong;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.271-274
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    • 2014
  • This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

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