• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Journal of Power Electronics
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• v.11 no.4
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• pp.533-541
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• 2011

The redundant operation of a parallel AC to DC converter via a serial communication bus is presented. The proposed system consists of three isolated CUK power factor correction modules. The controller for each converter is a dsPIC30F6010 microcontroller while a RS485 communication bus and the clock signal are used for synchronizing the data communication. The control strategy of the redundant operation relies on the communication of information among each of the modules, which communicate via a RS485 serial bus. This information is received from the communication checks of the converter module connected to the system to share the load current. Performance evaluations were conducted through experimentation on a three-module parallel-connected prototype, with a 578W load and a -48V dc output voltage. The proposed system has achieved the following: the current sharing is quite good, both the transient response and the steady state. The converter modules can perform the current sharing immediately, when a fault is found in another converter module. In addition, the transient response occurs in the system, and the output voltages are at their minimum overshoot and undershoot. Finally, the proposed system has a relatively simple implementation for the redundant operation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.3
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• pp.171-183
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• 2018

Herein, we show the design and fabrication of a serial-to-parallel converter (SPC) using the $0.25-{\mu}m$ GaAs pHEMT process. The serial-to-parallel converter is composed of four bits to control the four phase shifters used in the core chip. The SPC stores the received serial data signal to a register in the SPC and converts the stored data into the parallel data. Each converted output data can control four phase shifters. The size of the fabricated SPC is $1,200{\times}480{\mu}m^2$ and it uses two DC power supplies of 5 V and -3 V. The consumption current of each DC power supply is 7.1 mA for 5 V, and 2.1 mA for -3 V.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.2
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• pp.59-65
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• 2011

All-optical signal processing is expected to offer advantages in speed and power consumption against over electronics signal processing. It has a potential to solve the bottleneck issues of ultra-high speed communication network nodes. All-optical serial-to-parallel and parallel-to-serial data converters would make it possible to easily process the serial data information of a high-speed optical packet without optical-to-electronic-to-optical data conversion. In this paper, we explain the principle of simple and easily expandable all-optical serial-to-parallel and parallel-to-serial data converters based on Mach-Zehnder interferometers. We experimentally demonstrate these data converters at 10Gbit/s serial data rate. They are useful all-optical devices for the all-optical implementations of label decoding, self-routing, control of variable packets, bit-wise logical operation, and data format conversion.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.770-776
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• 2009

We propose and demonstrate an I/Q demodulator using four-port BPSK demodulator base on additive mixing and reflection-type phase shifter using hybrid technique. Previously, the conventional I/Q demodulator base on multiplicative or additive mixing method divides I/Q signal path from mixer to parallel-to-serial converter. In this paper, we propose new I/Q demodulator without dividing I/Q baseband signal path. The proposed schematic requires half size in implementation and half power consumption in baseband path compared with the conventional receiver. Also, the proposed receiver eliminates parallel-to-serial converter after data decoding. The proposed circuit has been successfully demodulated a QPSK signal with the L-band carrier frequency and 20 Mbps data rate.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2000.11a
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• pp.173-178
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• 2000

The time sharing type high frequency inverter using serial-parallel resonant to give VVVF function in the inverter used as power source of induction heating at high frequency is presented in this paper. This proposed inverter can reduce distribution of the switching current because of using the current of serial resonant circuit to the input current of the parallel one. The analysis of the proposed circuit is generally described by using the normalized parameters. Also, according to the calculated characteristics value, a method of the circuit design and operating characteristics of the inverter is proposed. In addition, this paper proves the validity of theoretical analysis through Simulation. This proposed inverter show that it can be practically used in future as power source system for induction heating application, DC-DC converter etc.

• Journal of Sensor Science and Technology
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• v.19 no.6
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• pp.469-474
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• 2010

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 um CMOS process and the measured total output jitter was less than 0.1 UIpp(unit-interval, peak-to-peak) over 20 kHz to 80 MHz bandwidth. The jitter of the CMU output only was measured as 0.2 ps,rms. The transmitter dissipates less than 200 mW from 1.5 V/2.5 V power supplies.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2002.11a
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• pp.293-296
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• 2002

This paper describes the instantaneous current resultant type load parallel high frequency resonant inverter consisting of three unit half-bridge serial and parallel resonant inverter can be used as power source of induction heating. This proposed inverter can reduce distribution of the switching current because of using the current of serial resonant circuit to the input current of the parallel one. The analysis of the proposed circuit is generally described by using the normalized parameters. Also, the principle of basic operating and the its characteristics are estimated by the parameters such as switching frequency($\mu$), load resistance(λ). Experimental results are presented to verify theoretical discussion. This proposed inverter will can be practically used as a power supply in various fields as induction heating application, DC-DC converter etc.