• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.4
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• pp.122-128
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• 2007

This paper represents the Input/Output (I/O) serial communication methods between overground and overhead controllers using a programmable logic controller (PLC). In general, the systems composed by overground and overhead controllers use exclusive serial communication units. This, however, has a demerit such as a high cost as well as some restrictions of the system itself. Thus, this paper suggests methods by I/O cards for data communication between overground and overhead controllers. In this system, there is no special card and it therefore has a lower cost and is more flexible than the exclusive serial communication unit.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.5
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• pp.229-235
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• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• Aerospace Engineering and Technology
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• v.6 no.2
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• pp.171-179
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• 2007

The Test Equipment for the upper stage of KSLV-I has following functions via umbilical cable interface; external power supply, command output such as discrete and analog, data acquisition, CS-I interface simulation for first stage of KSLV-I and RS-422 serial communication for PDU. The main purpose of UTE is the experiment or function verification of system-level upper stage. To realize this system, we used PXI control system. The UTE is consisted of the PXI control system, power supply, terminal block, internal harness, connector panel and so on. The software functions of UTE are classified by four blocks. These are Discrete/Analog I/O control, PDU RS-422 serial communication control, power supply GPIB control and UTE remote control. In this paper, we will describe the design on the hardware and software of UTE.

• Journal of the Korea Society of Computer and Information
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• v.25 no.6
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• pp.1-8
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• 2020

Communication between system modules is applied using the Modbus protocol in industrial sites including smart factories, industrial drones, building energy management systems, PLCs, ships, trains, and airplanes. The existing Modbus was used for serial communication, but the recent Modbus protocol is used for TCP/IP communication.The Modbus protocol supports RTU, TCP and ASCII, and implements and uses protocols in embedded systems. However, the transmission I/O devices for RTU, TCP, and ASCII-based protocols may differ. For example, RTU and ASCII communications transmit on a serial-based communication protocol, but in some cases, Ethernet TCP/IP transmission is required. In particular, since the C language (object-oriented) is used in embedded systems, the complexity of source code related to I/O registers increases. In this study, we designed software that can logically separate I/O functions from embedded devices, and designed the execution logic of each instance requiring I/O processing through a delegate class instance with Modbus RTU, TCP, and ASCII protocol generation. We designed and experimented with software that can separate communication I/O processing and logical execution logic for each instance.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.5
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• pp.259-265
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• 2016

In this paper, we present an architecture for the fault isolation by applying virtualization-based multi-stack technologies. We propose the simultaneous sharing and switching mechanism using virtualied serial communications. Each guest OS has its own virtual serial device. The distribution module provides communications between the guest OS's through the virtual serial devices and simultaneously detect the liveness of the guest OS. The suggested mechanism has been implemented in VirtualBox and shows satisfactory performance in transmission speed and data sharing capability with virtual RS232.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of IKEEE
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• v.19 no.4
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• pp.625-631
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• 2015

In this paper, an 8051 microcontroller with application-specific instructions and I/O ports for data transmission is designed. The designed microcontoller includes two UART ports and one SMBus port to control external devices and to transmit data with them. Application-specific instruction is developed and added to the instruction set to exploit these I/O ports. So the designed microcontroller can perform multi-device control and multi-byte transmission. Also, it can reduce the code size of the application program. Especially, the designed microcontroller does not stall and can execute other programs during data transmission, which significantly increases its efficiency. Synthesized in 0.18 um technology, the area overhead due to application-specific instructions was negligible. Operations of all instructions and I/O ports were verified to run correctly on a FPGA board.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.