• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.195-197
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• 2006

In this paper, an interface unit is designed to efficiently monitor transmission data in Controller Area Network(CAN)-based control systems. The CAN uses a serial multi master communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1Mbps. The interface unit is composed of a DSP controller which collects data on the CAN bus and transfers data to a personal computer via serial communication to save and display of interesting signals. The experimental system consists of three DSP controllers which represent electronic control units of a vehicle, an interface unit for analysing the data on the bus, and a graphic monitoring program coded on the Windows platform. The validity and the effectiveness of the proposed simple type of CAN interface unit are shown through the experimental results.

• ETRI Journal
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• v.24 no.6
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• pp.462-464
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• 2002

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• ETRI Journal
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• v.34 no.1
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• Proceedings of the KSR Conference
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• 2002.05a
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• pp.530-534
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• 2002

This paper show serial communication method in order to design how to interface between fault tolerant systems with redundancy. Problem has been in the method that fault tolerant system had switched of serial data with common switching device. This problem degrade reliability in itself and total system which is interfaced with that serial communication system. So Arbitration module of serial communication which is suggested in this paper can improve the reliability using voter algorithm which fault is detected passively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.622-628
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• 1996

This paper describes a new serial interface system which uses conventional 75 ohm coaxial cable. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3 VTR and HDTV Receiver. The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are required. This serial data transfer technique is thoroughly tested and utilied in the data transmission/reception between systems more than 200 feet apart. It is also cost effective because it does not require RF PLL, SCRAMBLING, and NRZI hardware.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.35-40
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• 2023

In this paper, a serial wireless LAN virtual communication module that allows microprocessors to communicate wirelessly with other peripheral devices is developed as part of a study to build an online virtual experiment system that allows them to practice virtually anytime, anywhere in microprocessor application education in electrical and electronic control engineering. The developed module is connected to the microprocessor in the virtual experiment system through serial interface. The serial data is sent to and received from peripheral devices through the wireless LAN interface of the host computer where the virtual experiment software is being performed. In order to verify the function of the developed serial wireless LAN virtual communication module, experiments were conducted in which a microprocessor in the virtual experiment system exchanged data with an Android smartphone through a wireless LAN interface of a host computer. The developed serial wireless LAN communication module is expected to enable virtual microprocessors to communicate with surrounding real devices through wireless LAN, which can be efficiently used in microprocessor application education.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.552-560
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• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1814-1819
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• 1996

This paper describes a dnw serial interface system which uses comma free code. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3VTR and HDTV Receiver.The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are requeired. This serial data trasfer technique is possible the error detection and the self synchronization, also easy edge insertion for PLL control. It is also cost effective because is does not requeire RF PLL, scrambling, and NRZI hardware.