• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.2
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• pp.232-239
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• 2016

Recently, in order to increase the efficiency and mission success rate of UAVs (Unmanned Aerial Vehicles), the necessity for formation flights is increased. In general, GPS (Global Positioning System) is used to obtain the relative position of leader with respect to follower in formation flight. However, it can't be utilized in environment where GPS jamming may occur or communication is impossible. Therefore, in this study, monocular vision is used for measuring relative position. General PC-based vision processing systems has larger size than embedded systems and is hard to install on small vehicles. Thus FPGA-based processing board is used to make our system small and compact. The processing system is divided into two blocks, PL(Programmable Logic) and PS(Processing system). PL is consisted of many parallel logic arrays and it can handle large amount of data fast, and it is designed in hardware-wise. PS is consisted of conventional processing unit like ARM processor in hardware-wise and sequential processing algorithm is installed on it. Consequentially HW/SW co-designed FPGA system is used for processing input images and measuring a relative 3D position of the leader, and this system showed RMSE accuracy of 0.42 cm ~ 0.51 cm.

• Journal of Gifted/Talented Education
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• v.19 no.2
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• pp.241-260
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• 2009

The purpose of this study was to contrast young gifted children with ordinary young children in K-ABC profile. The subject were 51 young gifted children and 51 ordinary young children, 2 to 4 years of age. Data of children's K-ABC profile were analyzed by Correlation and Crosstabs. The main results of this study were as follows: First, in the case of ordinary young children, there were significant positive correlation among 'Mental Processing Composite' and all sub-tests of mental processing composite except 'face memory' test, 'Achievement Scale'. In young gifted children, there were significant positive correlation among 'Mental Processing Composite' and just four sub-tests of mental processing composite, and there were no significant correlation between 'Mental Processing Composite' and 'Achievement Scale'. Second, there were no significant differences among all sub-tests' strength and weakness in young gifted children and ordinary young children. Third, young gifted children got higher score in 'Sequential Processing Scale' and 'Mental Processing Composite' than 'Achievement Scale'. But in ordinary young children, there were no significant differences among all K-ABC' sub-scales.

• The Transactions of the Korea Information Processing Society
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• v.4 no.4
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• pp.1035-1045
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• 1997

It is important to understand how we can deal with doements for the modeling of neural networks when we are unbestigating the dynamical performance and the information procoessing capabilitids.The information procewssing capabkities of model neural networks will change for different response, synaptic weights or learning rules. Using the staritical neurodyamics method, we evalute the capabikities of neural networks in order to understand the basic conept ofr parallel distributed processing. In this paper, we explain the reuslts of theoretical anaysis of the effests of the hysteretic property on the performance of wuquential associative neral networks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.150-161
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• 2012

Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.8
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• pp.778-785
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• 2009

This paper presents a Gabor texture feature extraction method for classification of discolored Metal pad images using GPU(Graphics Processing Unit). The proposed algorithm extracts the texture information using Gabor filters and constructs a pattern map using the extracted information. Finally, the golden pad images are classified by utilizing the feature vectors which are extracted from the constructed pattern map. In order to evaluate the performance of the Gabor texture feature extraction algorithm based on GPU, a sequential processing and parallel processing using OpenMP in CPU of this algorithm were adopted. Also, the proposed algorithm was implemented by using Global memory and Shared memory in GPU. The experimental results were demonstrated that the method using Shared memory in GPU provides the best performance. For evaluating the effectiveness of extracted Gabor texture features, an experimental validation has been conducted on a database of 20 Metal pad images and the experiment has shown no mis-classification.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.21 no.8
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• pp.1024-1033
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• 1997

The past several years have witnessed an ever-increasing acceptance and adoption of parallel processing, both for high performance scientific computing as well as for more general purpose applications. Furthermore with increasing needs to perform the complex flow calculations in an efficient manner, the use of the message passing model on distributed networks has emerged as an important alternative to the expensive supercomputers. This work attempts to provide a generic framework to enable the parallelization of all CFD-related works using the master-slave model. This framework consists of (1) input geometry, (2) domain decomposition, (3) grid generation, (4) flow computations, (5) flow visualization, and (6) output display as the sequential components, but performs computations for (2) to (5) in parallel on the workstation clustering. The flow computations are parallized by having multiple copies of the flow-code to solve a PDE on different spatial regions on different processors, while their flow data are exchanged across the region boundaries, and the solution is time-stepped. The Parallel Virtual Machine (PVM) is used for distributed communication in this work.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.57-64
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• 2000

We describe a parallel implementation for the large-eddy simulation(LES) of stratified and rotating turbulence based on MPI. The parallelization strategy is specified by eliminating the tridiagonal solver with explicit method and by domain decompositions for solving the poisson equation. In this simulation we have run on CRAY-T3E under the message passing platform MPI with a various domain decomposition and the scalability of this parallel code of LES are also presented. The result shows that we can gain up to 16 times faster speed up on 64 processors with xyz-directional domain decomposition and scalable up to $128{\times}128{\times}$ which processing time is almost similar to that of $40{\times}40{\times}40$ on a single processor machine with a sequential code.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.388-394
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• 1999

This paper is concerned with an application of Parallel Genetic Algorithms(PGA) to optimal econmic load dispatch(ELD) in power systems. The ELD problem is to minimize the total generation fuel cost of power outputs for all generating units while satisfying load balancing constraints. Genetic Algorithms(GA) is a good candidate for effective parallelization because of their inherent principle of evolving in parallel a population of individuals. Each individual of a population evaluates the fitness function without data exchanges between individuals. In application of the parallel processing to GA, it is possible to use Single Instruction stream, Multiple Data stream(SIMD), a kind of parallel system. The architecture of SIMD system need not data communications between processors assigned. The proposed ELD problem with C code is implemented by SIMSCRIPT language for parallel processing which is a powerfrul, free-from and versatile computer simulation programming language. The proposed algorithms has been tested for 38 units system and has been compared with Sequential Quadratic programming(SQP).

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.885-888
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• 2018

This paper researches a way of detecting fish robots moving in an aquarium. The fish robot was designed and developed for interactions with humans in aquariums. It was studied merely to detect a moving object in an aquarium because we need to find the positions of moving fish robots. The intention is to recognize the location of robotic fish using an image processing technique and a video camera. This method is used to obtain the velocity for each pixel in an image, and assumes a constant velocity in each video frame to obtain positions of fish robots by comparing sequential video frames. By using this positional data, we compute the distance between fish robots using a mathematical expression, and determine which fish robot is leading and which one is lagging. Then, the lead robot will wait for the lagging robot until it reaches the lead robot. The process runs continuously. This system is exhibited in the Busan Science Museum, satisfying a performance test of this algorithm.