• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.2
• /
• pp.15-21
• /
• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Proceedings of the Korea Air Pollution Research Association Conference
• /
• 2003.05b
• /
• pp.47-48
• /
• 2003

This new family of portable real time SEQUENTIAL MOBILITY PARTICLE COUNTER and SIZER (SMPS+C) is designed for mobility and easy field use. An integrated battery assures hours of operation, a data logger system storage of all optioned results and a user friendly powerful software easy operation. This technology not only simplifies the SMPS operation, but it permits new on site application monitoring up to a remote wireless telephone operation. (omitted)

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.7
• /
• pp.458-461
• /
• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.4
• /
• pp.39-48
• /
• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of Institute of Control, Robotics and Systems
• /
• v.12 no.12
• /
• pp.1163-1168
• /
• 2006

Manufacturing technology for the production of high value-added fine chemical products is emphasized and getting more attention as the diversified interests of customers and the demand of high quality products are getting bigger and bigger everyday. Thus, the development of advanced batch processes, which is the preferred and most appropriate way of producing these types of products, and the related technologies are becoming more important. Therefore, high-precision batch distillation is one of the important elements in the successful manufacturing of fine chemicals, and the importance of the process operation strategy with quality assurance cannot be overemphasized. Accordingly, proposing a process structure explanation and operation strategy of such processes including batch processes and batch distillation would be of great value. We investigate optimal operation strategy and production planning of multi-purpose plants consisting of batch processes and batch distillation for the manufacturing of fine chemical products. For the short-term scheduling of a sequential multi-purpose batch plant consisting of batch distillation under MPC and UIS policy, we proposed a MILP model based on a priori time slot allocation. Also, we consider that the waste product of being produced on batch distillation is recycled to the batch distillation unit for the saving of raw materials. The developed methodology will be especially useful for the design and optimal operations of multi-purpose and multiproduct plants that is suitable for fine chemical production.

• Journal of the Korea Society of Computer and Information
• /
• v.24 no.8
• /
• pp.9-17
• /
• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.10
• /
• pp.1354-1360
• /
• 2013

In transmission system, reclosing scheme is very useful method to improve continuity of power supply and reliability of system. Especially, high speed reclosing which is used generally in transmission systems has a benefit improving transient stability. However, the reclosing can jeopardize the stability under the condition having high difference of voltage phase angle between both ends. Thus, this paper proposes optimal sequential reclosing scheme to improve transient stability due to reclosing operation. The optimal sequential reclosing is that each phase is closed sequentially considering transient energy. In this paper, 345kV and 154kV transmission system is modeled using EMTP (ElectroMagnetic Transient Program) to verify the performance and effectiveness of optimal sequential reclosing on transient stability. Also, Integral Square Error(ISE) method is used to assess the transient stability.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.168-176
• /
• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• Proceedings of the KIEE Conference
• /
• 2000.07d
• /
• pp.3088-3090
• /
• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.4
• /
• pp.96-104
• /
• 1998

In this paper, the circuit of DTCNN designed using dilation and erosion operation, a basic operation of gray-scale morphology, also each cell designed PE in order to having extension using the local connectivity. In this PE design, connection of between cell and cell become simple. And it is realized to easily VLSI realization as well as to circuit to be parallel processing. As the resutls of simulations, the proposed method was verified to improved more operation speed than the sequential data processing, parallel processing DTCNN was implemented in a 0.8.mu.m CMOS technology using COMPASS Tool.