• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.54-61
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• 1998

Ladder Diagram(LD) is the most extensively used among Programmable Logic Controller(PLC) standard languages for the design of process control system with PLC. But LD has the disadvantages for data processing and maintenance. On the other hand, there is full support for describing sequences so that complete sequential behavior can be easily broken down using a concise graphical language called Sequential Function Chart(SFC). Inspite of those characteristics, SFC is not suitable for describing interlock logic. In this paper, we propose the method for implementing interlock logic by using conventional SFC compiler and verify the effectiveness by applying proposed scheme to the In-Line Spin Coater.Coater.

• Journal of Digital Convergence
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• v.20 no.5
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• pp.443-451
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• 2022

The paper delves into the elaborate intermediating mechanisms of the association between coaching leadership and safety behavior. To do that, this study tried to identify the sequential mediating effects of employee's meaningfulness of work and perceived organizational support between coaching leadership and safety behavior. By utilizing 3-wave survey data from 250 employees in Korean companies with conducting structural equation modeling(SEM), this paper found that coaching leadership had a positive influence on safety behavior through sequential mediating effect of employee's meaninfulness of work and perceived organizational support.

• Review of Korea Contents Association
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• v.18 no.1
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• pp.12-17
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• 2020

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.1-10
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• 2008

The problem of controlling asynchronous sequential machines is addressed in this paper. Corrective control means to make behavior of an asynchronous sequential machine equal to that of a given model. The main objective is to develope a corrective controller, especially when a model is given as nondeterministic, or a set of reference models. The structure of corrective control system for asynchronous sequential machines is addressed first, followed by description of nondeterministic models. Then, we propose a method for analyzing reachability of asynchronous machines and nondeterministic models. Proposed methods are demonstrated in an example.

• Proceedings of the KIEE Conference
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• 1986.07a
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• pp.486-489
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• 1986

The transition diagram, as well as the regular expression, can be used as a formal description for a language acceptable by a finite automaton or for the behavior of a sequential switching circuit. But, if we are given one of these two descriptions, we shall find that it is not easy to get the other counterpart description. This paper is to show an easy method to find the equivalet regular expression from the transition diagram, by the aid of a graph-transformation technique.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.698-701
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• 2002

Subspace analysis (which includes PCA) seeks for feature subspace (which corresponds to the eigenspace), given multivariate input data and has been widely used in computer vision and pattern recognition. Typically data space belongs to very high dimension, but only a few principal components need to be extracted. In this paper I present a fast sequential algorithm for subspace analysis or tracking. Useful behavior of the algorithm is confirmed by numerical experiments.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.1
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.04a
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• pp.87-94
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• 2004

A number of approximate techniques have been developed to calculate the eigenvalues in a reduced manner. These schemes approximate the lower eigenvalues that represent the global behavior of the structures. In general, sequential elimination has been widely used with reliability. But it takes excessively large amount of time to construct a reduced system. The present study proposes two-level condensation scheme(TLCS). In the first step, the candidate elements are selected by element-level energy estimation. In the second step, master degrees of freedom are selected by sequential elimination from the candidate degrees of freedom linked to the selected elements in the first step. Numerical examples demonstrate that the proposed method saves computational cost effectively and provides a reduced system which predicts the accurate eigenvalues of global system.