• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2724-2729
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• 2010

This paper presents a method of constructing the sequential digital systems over finite fields. We assign all elements in finite fields to digit codes using mathematical properties of finite fields. Also, we discuss the operational characteristics and properties of the building block T-gate which is used to implement the sequential digital systems over finite fields. Then, we implemented sequential digital systems without feed-back. The sequential digital systems without feed-back is constructed as following steps. First, we assign the states in state-transition diagram to state digit codes, then obtain the state function and predecessor table which is explaining the relationship between present states and previous states. Next, we obtained the next-state function from state function and predecessor table. Finally we realize the circuit using T-gate and decoder. The proposed method is more efficiency and systematic than previous method.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.278-281
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• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.273-275
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• 2006

Ladder Diagram(LD) is the most widely utilized among many sorts of existing programs using for the design of process control system. But it is very difficult to grasp sequential flow of control logic. In this paper, we proposed the method that we can control a lot of blocks. We used PLC in process control system. And, in order to design we used Sequential Function Chart(SFC). In this paper, we proposed the method of block contro. and confirmed feasibility through a simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.54-61
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• 1998

Ladder Diagram(LD) is the most extensively used among Programmable Logic Controller(PLC) standard languages for the design of process control system with PLC. But LD has the disadvantages for data processing and maintenance. On the other hand, there is full support for describing sequences so that complete sequential behavior can be easily broken down using a concise graphical language called Sequential Function Chart(SFC). Inspite of those characteristics, SFC is not suitable for describing interlock logic. In this paper, we propose the method for implementing interlock logic by using conventional SFC compiler and verify the effectiveness by applying proposed scheme to the In-Line Spin Coater.Coater.

• Journal of the Korean Institute of Gas
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• v.16 no.6
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• pp.41-47
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• 2012

There are PFD(Process Flow Diagram) and P&ID(Piping and Instrument Diagram) for designing and managing chemical process efficiently. They provide the operation condition and equipment specifications of chemical process, but they do not provide the reliability of chemical process. Therefore, in this study, Reliability Flow Diagram(RFD) which provide the cycle and time of preventive maintenance has been developed using Directed Graph Analysis methodology. Directed Graph Analysis methodology is capable of assessing the reliability of chemical process. It models chemical process into Directed Graph with nodes and arcs and assesses the reliability of normal operation of chemical process by assessing Directed Graph sequential. In this paper, the chemical process reliability transition according to operation time was assessed. And then, Reliability Flow Diagram has been developed by inserting the result into P&ID. Like PFD and P&ID, Reliability Flow Diagram provide valuable and useful information for the design and management of chemical process.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.11
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• pp.939-943
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• 2001

PLC(programmable Logic Controller)s essential components of modern automation systems encompassing almost every industry. Ladder Diagrams (LD) have been widely used in the design of such PLC since the LD is suitable for the modeling of the sequential control system. However, the synthesis of LD itself mainly depends on the experience of the industrial engineer, which may results in unstructured or inflexible design. Hence, in this paper, we propose a ladder diagram conversion algorithm which systematically produces LDs for PLCs based on discrete event models to enhance the structured and flexible design mechanism.

• Proceedings of the KSMRM Conference
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• 2002.11a
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• pp.15-29
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• 2002

MRI에서 펄스 시퀀스(pulse sequence)란 고주파 RF(radiofrequency) 펄스 및 경사자장(gradient) 펄스를 가하고 MR 신호를 획득하는 순서를 시간대별로 도식화 한 pulse diagram을 이야기한다. 이러한 pulse sequence는 실제로 영상을 획득하기 위한 RF amplifier, gradient amplifier 등의 하드웨어를 순차적(sequential)으로 구동하는 역할을 한다. 따라서 이러한 pulse sequence는 현재 임상적으로 사용되는 다양한 영상기법들을 이해하는데 필수적이다.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.237-239
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• 1983

본 논문은 어떤 비동기적인 제어계가 상태 천이도(transition diagram)로 표현되기만 하면 이 입력으로부터 직접 비동기 순차회로를 구성 할 수 있는 알고리즘을 제시하고 있다. 이로써 비동기 회로를 쉽게 하드웨어로 실현 할수 있도록 하였다.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.