• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.699-702
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• 1998

This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using $0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.1-1
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• 2001

DRAM에서 셀 캐패시터의 누설 전류 영향을 고려하여 소프트 에러율을 예측하였다. DRAM의 동작 과정에서 누설 전류의 영향으로 셀 캐패시터는 전하량이 감소하고, 이에 따른 소프트 에러율을 DRAM의 각 동작 모드에 대하여 계산하였다. 누설 전류가 작을 경우에는 /bit mode가 소프트 에러에 취약했지만, 누설전류가 커질수록 memory 모드가 소프트 에러에 가장 취약함을 보였다. 실제 256M급 DRAM의 구조에 적용하여, 셀 캐패시턴스, bit line 캐패시턴스, sense amplifier의 입력 전압 감도들이 변화할 때 소프트 에러에 미치는 영향을 예측하였고, 이 결과들은 차세대 DARM 연구의 최적 셀 설계에 이용될 수 있다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.511-513
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• 1998

본 연구는 영상소자의 감도를 향상 시키기 위하여 전압 분배 회로를 가진 감지 회로를 설계하였다. 전압분배 회로는 NMOSFET과 Poly 저항의 두 경우로 설계하였으며 감지 회로에 흐르는 전류는 전압 분배 회로를 NMOSFET으로 설게하였을때가 Poly 저항으로 구성한 경우보다 적게 흐르며 감도 특성도 좋은 것으로 나타났다. 또한 poly 저항보다 NMOSFET을 이용한 전압 분배 회로가 동작 주파수에 따른 특성이 우수하였다.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.65-69
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• 1998

본 연구는 전하 결합 영양소자에서 감지회로의 특성을 향상시키기 위하여 N형 MOSFET과 Polysilcon 저항에 의한 전압 분배 회로를 가진 감지회로를 설계하였다. 감지회 로에 흐르는 전류는 전압분배회로를 N형 MOSFET으로 설계하였을때가 Polysilicon 저항으 로 설계한 경우보다 감도 특성도 좋은 것으로 나타났다. 이는 전압분배회로를 Polysilicon으 로 설계한 경우보다 N형 MOSFET으로 설계하였을 때 동작 주파수가 높을수록 전압이득 특성이 우수하기 때문이다. 감지회로에 흐르는 전류는 전압분배회로를 N형 MOSFET으로 설계하였을 때 2mA 정도를 나타내고 polysilcon으로 설계하였을 때 4mAwjd도로 나타났다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.221-226
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• 2012

In this paper, wideband two-stage amplification stage was designed, fabricated and evaluated. The proposed amplification stage with a novel gain control method have a high gain, low noise and high linearity performance. It is consisted of common emitter amplifier as the first stage, cascode gain control amplifier as second stage and power detector which sense the received signal strength. The proposed amplification stage shows a total gain of 29 dB~37 dB, noise fiugre of 1.5 dB at operating band and high linearity performance as the IMD (third intermodulation distortion) level is below the noise level of the measurement equipment at the control voltage 2.0 V generated from power detector under the strong electric field condition.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.517-525
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• 2011

Differential Vibrating Accelerometer(DVA) is a small and accurate resonant device to sense the change in natural frequency in presence of acceleration input. Both mathematical modeling for the electromechanical dynamics and experimental investigation on the structural characteristics are necessary for effective designs of precision controller and high Q-factor structure. In this paper, electromechanical modeling of the resonator of DVA, electrode module, and pre-amplifier is presented. The presented method is experimentally verified by measuring the resonance frequency, effective mass, effective stiffness and Q-factor. The direct comparison of the calculated displacement and the actual pre-amplifier of DVA also indicates the effectiveness of this study.

• Journal of Digital Contents Society
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• v.19 no.4
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• pp.615-620
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• 2018

Evaluation of clinical usefulness of current perception threshold test and vibration sense perception threshold test in diagnosing the diabetic poly-neuropathy patients is one of the diagnosis methods for diabetic poly-neuropathy. Up to the present, some diagnostic methods were used for diabetic poly neuropathy patients. For example, there are neuropathy impairment score test of lower limbs, nerve conduction test, cooling detection threshold test, heat-pain threshold test and so on. However, most of the above tests require very expensive cost and take a lot of time in test. In this paper, a new apparatus estimating vibration sense ability is introduced. For this purpose, the VCM(voice coil motor) stimulating patient's peripheral nerve and current amplifier were manufactured. Also, softwares sensing and driving the vibration detection threshold test in order to measure the quantitative vibration sensory levels in diabetic poly-neuropathy patients were developed.