• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.57-68
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• 2004

Recently, Radio Frequency Identification (RFID) systems stands in the spotlight of industry as a common and useful tool in manufacturing, supply chain management (SCM) and stock management. In the near future, low-cost RFID Electronic Product Code; (EPC) or smart-labels may be a practical replacement for optical barcodes on consumer items. However, manufacturing cheap and small RFID tags, and developing secure RFID authentication Protocols are problems which need to be solved. In spite of advances in semiconductor technology, computation and storage ability of the tag are so limited that it is difficult and too expensive to apply existing crypto-systems to RFID tags. Thus it is necessary to create a new protocol which would require less storage space and lower computation costs and that is secure in the RFID system's environments. In this paper, we propose a RFID authentication protocol that is secure against location tracking and spoofing attacks. Our protocol can be used as a practical solution for privacy protection because it requires less computations in database than the previous RFID authentication protocol.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.232-240
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• 2022

A variable vacuum capacitor (VVC), which is a variable element, is used to match impedance in plasma that changes with various impedance values, and its use is expanding with the rapid growth of the semiconductor business. Since VVCs have to secure insulation performance and vary capacitance within a compact size, electrode design and manufacturing are very important; thus, various technologies such as part design and manufacturing technology and vacuum brazing technology are required. In this study, based on the model of an advanced foreign company that is widely used for impedance matching in the manufacture of semiconductors and displays, a VVC that can realize the same performance was developed. The electrode part was designed, the consistency was confirmed through analysis, and the precision of capacitance was improved by designing a cup-type electrode to secure the concentricity of the electrode. As a result of the evaluation, all requirements was satisfied. We believe that self-development will be possible if satisfactory responses are received through evaluation by VVC consumers in the future.

• Journal of the Korea Society for Simulation
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• v.26 no.4
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• pp.35-41
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• 2017

With the advances in Internet over Things, the demand in diverse electronic devices such as mobile phones and sensors has been rapidly increasing and boosting up the researches on those products. Semiconductor materials, devices, and fabrication processes are becoming more diverse and complicated, which accompanies finding parameters for an optimal fabrication process. In order to find the parameters, a process simulation before fabrication or a real-time process control system during fabrication can be used, but they lack incorporating the feedback from post-fabrication data and compatibility with older equipment. In this research, we have developed an artificial intelligence based simulator, which finds parameters for an optimal process and controls process equipment. In order to apply the control concept to all the equipment in a fabrication sequence, we have developed a prototype for a manipulator which can be installed over an existing buttons and knobs in the equipment and controls the equipment communicating with the AI over the Internet. The AI is based on the deep learning to find process parameters that will produce a device having target electrical characteristics. The proposed simulator can control existing equipment via the Internet to fabricate devices with desired performance and, therefore, it will help engineers to develop new devices efficiently and effectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.241-241
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• 2012

Semiconductor industry has been taking the advantage of improvements in process technology in order to maintain reduced device geometries and stringent performance specifications. This results in semiconductor manufacturing processes became hundreds in sequence, it is continuously expected to be increased. This may in turn reduce the yield. With a large amount of investment at stake, this motivates tighter process control and fault diagnosis. The continuous improvement in semiconductor industry demands advancements in process control and monitoring to the same degree. Any fault in the process must be detected and classified with a high degree of precision, and it is desired to be diagnosed if possible. The detected abnormality in the system is then classified to locate the source of the variation. The performance of a fault detection system is directly reflected in the yield. Therefore a highly capable fault detection system is always desirable. In this research, time series modeling of the data from an etch equipment has been investigated for the ultimate purpose of fault diagnosis. The tool data consisted of number of different parameters each being recorded at fixed time points. As the data had been collected for a number of runs, it was not synchronized due to variable delays and offsets in data acquisition system and networks. The data was then synchronized using a variant of Dynamic Time Warping (DTW) algorithm. The AutoRegressive Integrated Moving Average (ARIMA) model was then applied on the synchronized data. The ARIMA model combines both the Autoregressive model and the Moving Average model to relate the present value of the time series to its past values. As the new values of parameters are received from the equipment, the model uses them and the previous ones to provide predictions of one step ahead for each parameter. The statistical comparison of these predictions with the actual values, gives us the each parameter's probability of fault, at each time point and (once a run gets finished) for each run. This work will be extended by applying a suitable probability generating function and combining the probabilities of different parameters using Dempster-Shafer Theory (DST). DST provides a way to combine evidence that is available from different sources and gives a joint degree of belief in a hypothesis. This will give us a combined belief of fault in the process with a high precision.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.1
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• pp.18-26
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• 2016

The semiconductor industry is one of the key industries of Korea, which has continued growing at a steady annual growth rate. Important technology for the semiconductor industry is high integration of devices. This is to increase the memory capacity for unit area, of which key is photolithography. The photolithography refers to a technique for printing the shadow of light lit on the mask surface on to wafer, which is the most important process in a semiconductor manufacturing process. In this study, the width and step-height of wafers patterned through this process were measured to ensure uniformity. The widths and inter-plate heights of the specimens patterned using photolithography were measured using transmissive digital holography. A transmissive digital holographic interferometer was configured, and nine arbitrary points were set on the specimens as measured points. The measurement of each point was compared with the measurements performed using a commercial device called scanning electron microscope (SEM) and Alpha Step. Transmission digital holography requires a short measurement time, which is an advantage compared to other techniques. Furthermore, it uses magnification lenses, allowing the flexibility of changing between high and low magnifications. The test results confirmed that transmissive digital holography is a useful technique for measuring patterns printed using photolithography.

• Analytical Science and Technology
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• v.19 no.6
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• pp.535-543
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• 2006

Being used widely in semiconductor and display manufacturing, $NF_3$ is internationally considered as one of the regulated compounds in emission. Numerous companies have been continuously trying to reduce the emissions of $NF_3$ to comply with the global environmental regulation. This work is made to report the destruction and removal efficiency (DRE) of electrically heated scrubbers and the use rate in process chambers installed in three main LCD manufacturing companies in Korea. As the measurement techniques for $NF_3$ emission, mass flow controlled helium gas was continuously supplied into the equipment by which scrubber efficiency is being measured. The partial pressures of $NF_3$ and helium were accurately measured for each sample using a mass spectrometer, as it is emitted from inlet and outlet of the scrubber system. The results show that the DRE value for electrically heated scrubbers installed before 2004 is less than 52 %, while that for the new scrubbers modified based on measurement by scrubber manufacturer has been sigificentely improved upto more than 95 %. In additon, we have confirmed the efficiency depends on such variables as the inlet gas flow rate, water content, heater temperature, and preventative management period. The use rates of $NF_3$ in process chambers were also affected by the process type. The use rate of radio frequency source chambers, built in the $1^{st}$ and $2^{nd}$ generation process lines, was determined to be less than 75 %. In addition, that of remote plasma source chambers for the $3^{rd}$ generation was measured to be aboove 95 %. Therefore, the combined application of improved scrubber and the RPSC process chamber to the semiconductor and display process can reduce $NF_3$ emmision by 99.95 %. It is optimistic that the mission for the reduction of greenhouse gas emission can be realized in these LCD manufacturing companies in Korea.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.923-925
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• 2002

The existing contactless inductive coupler has many problems because of its large volume and high level of exciting current, so a new contactless inductive coupler is being required under the circumstances and the load requirement. For a contactless inductive coupler in the manufacturing equipment of semiconductor, the coupler's efficiency is low because of its small magnetic inductance and large leakage inductance. Moreover, the high frequency switching to increase energy density per unit volume increases the iron loss and the eddy current loss, so it must be considered deeply when selecting core materials. Therefore, this paper presents core materials and shape to improve the performance of the contactless inductive coupler according to the coil positions.

• Journal of Mechanical Science and Technology
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• v.20 no.9
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• pp.1492-1501
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• 2006

A transportation system of single wafer has been developed to be applied to semiconductor manufacturing process of the next generation. In this study, the experimental apparatus consists of two kinds of track, one is for propelling a wafer, so called control track, the other is for generating an air film to transfer a wafer, so called transfer track. The wafer transportation speed has been evaluated by the numerical and the experimental methods for three types of nozzle position a..ay (i.e., the front-, face- and rear-array) in an air levitation system. Test facility for 300mm wafer has been equipped with two control tracks and one transfer track of 1500mm length from the starting point to the stopping point. From the present results, it is found that the experimental values of the wafer transportation speed are well in agreement with the computed ones. Namely, the computed values of the maximum wafer transportation speed $V_{max}$ are slightly higher than the experimental ones by about $15{\times}20%$. The disparities in $V_{max}$ between the numerical and the experimental results become smaller as the air velocity increases. Also, at the same air flow rate, the order of wafer transportation speeds is : $V_{max}$ for the front-array > $V_{max}$ for the face-array > $V_{max}$ for the rear-array. However, the face-array is rather more stable than any other type of nozzle array to ensure safe transportation of a wafer.

• ETRI Journal
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• v.34 no.6
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.