• Journal of the Korea Society for Simulation
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• v.26 no.1
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• pp.69-75
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• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.27-32
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• 2011

In this study, we have investigated the power conversion efficiency of organic solar cells utilizing conjugated polymer/fullerene bulk-hetero junction(BHJ) device structures. We have fabricated poly(3-hexylthiophene)(P3HT), poly[2methoxy-5-(3',7'-dimethyloctyl-oxy)-1-4-phenylenevinylene] as an electron donor, [6,6]-phenyl $C_{61}$ butyric acid methylester(PCBM-$C_{61}$)as an electron acceptor, and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS) used as a hole injection layer(HIL), after fabricated active layer, between active layer and metal cathode(Al) deposited LiF interlayer(5 nm). The properties of fabricated organic solar cell(OSC) devices have been analyzed as a function of different thickness. The electrical characteristics of the fabricated devices were investigated by means J-V, fill factor(FF) and power conversion efficiency(PCE). We observed the highest PCEs of 0.628%(MDMO-PPV:PCBM-$C_{61}$) and 2.3%(P3HT:PCBM-$C_{61}$) with LiF inter-layer at the highest thick active layer, which is 1.3times better than the device without LiF inter-layer.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.4
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• pp.408-411
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• 2008

As to this research is new structure of the semiconductor substrate heating apparatus. The fast thermoresponsive according to the direct heating structure of the heating plate layer adhering closely to the floor side of a substrate and the fast heat loss minimization can be accomplished. Moreover, the contact area of the sheath heater, which is the heating plate layer built-in heating apparatus, is increased, so that it has more heating valid area. For this, it adheres closely to the substrate, in which the photosensitive film is coated and the heating plate layer, adhering closely to the floor side of a substrate the mica layer which adheres closely to the floor side of the upper heating plate layer in order to minimize an insulation and heat loss, and the lower part of the mica layer and it is comprised of the floor plate layer. The heating plate layer forms the continued groove portion over the floor side whole. The sheath heater for heating a substrate is inserted with the groove portion and the heating plate layer is comprised. It is confirmed that by using the new substrate heating structure, the temperature change of the heating plate against the time is observed. Then, there is the electric power saving effect of about 40% in comparison with the existing method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1528-1534
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• 1989

Photoeffects at the p-GaP semiconductor/CsNO3 electrolyte interface were investigated in terms of their current-voltage characteristics. The photoeffects at the semiconductor-electrolyte interfaces and their photocurrent variations are verified using Ar ion laser and continuous cyclic voltammetric methods. The mechanism of charge transfer at the photogeneration in the depletion layer rather than the photodecomposition of the p-GaP semiconductor electrode surface and/or the water photoelectrolysis. The adsorption of Cs+ ions at the interface is physical adsorption.

• Journal of Sensor Science and Technology
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• v.33 no.2
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• pp.117-117
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• 2024

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.141-157
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• 2001

Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.11-17
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• 2004

This research has been progressed for adhesive improvement of the Polyimide/Buffer layer/Cu at the COF(Chip On Film) which induced as the alternative plan about high concentration of a circuit or substrates according to demands of miniaturization and high efficiency of various electronic equipment. RF plasma equipment was applied to when plama pretreatment was performed for improvement of adhesive strength of PI and Cr as the buffer layer. Experimental fluents were a species of the buffer layer, depositied time and the ratio of $O_2$/Ar when performed to plasma pretreatment. The results are that Ni was superior to Cr at peel test according to a species of the buffer layer, peel strength and Cu THK were showed proportional relation to deposition structure of the same buffer layer and sample of the Cr depositied time(30 sec) and Cu depositied time(20 min) was showed good adhesion to peel test according to Cr's depositied time and Cu's depositied time. When perform PI's plasma pretreatment peel strength and $O_2$/Ar ratio were showed proportional relation. But $O_2$/Ar(2/5) was best condition since then decreased.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.119-124
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• 2022

Top emission organic light-emitting diode (TEOLED) is commonly used because of high efficiency and good color purity than bottom - emission organic light-emitting device (BEOLED). Unlike BEOLED, TEOLED contain semitransparent metal cathode and capping layer. Because there are many characteristics to consider just simple thickness change, optimizing organic thickness of TEOLED for microcavity is difficult. So, in this study, we optimized Device capping layer at unoptimized micro-cavity structure TEOLED device. And we compare only capping layer with unoptimized microcavity structure can overcome optimized micro-cavity structure device. We used previous our optimized micro-cavity structure to compare each other. As a result, it has been found that the efficiency can be obtained almost the same or higher only capping layer, which is stacked on top of the device and controls only the thickness and refractive index, without complicated structural calculations. This means that higher efficiencies can be obtained more easily in laboratories with limited organic materials or when optimizing new structures etc.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.65-70
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• 2024

Using a computational fluid dynamics(CFD) simulation tool, we have provided a coating guideline for slot-die coating with a double layer slot die head. We have analyzed the fluid dynamics in terms of the coating speed, flow rate ratio, and viscosity ratio, which are critical for the stability of coating meniscus. We have identified the common coating defects such as break-up, air entrainment, and leakage by varying the coating speeds. The flow rate ratio is the critical parameter determining the wet film thickness of the top and bottom layers. It is shown that when the flow rate ratio exceeds or equals 1.8, air entrainment occurs due to insufficient hydraulic pressure in the bottom layer, even though the total flow rate remains constant. Furthermore, we have found that the flow of the bottom layer is significantly affected by the viscosity of top layer. The viscosity ratio of 4 or higher obstructs the flow of the bottom layer due to the increased hydraulic resistance, resulting in leakage. Finally, we have demonstrated that as the viscosity ratio increases from 0.1 to 10, the maximum coating speed rises from 0.4 mm/s to 1.6 mm/s, and the minimum wet film thickness decreases from 800 ㎛ to 200 ㎛.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.243-247
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• 2012

The paper focuses on an anti-reflection (AR) coating deposited by PECVD in silicon solar cell fabrication. AR coating is effective to reduce the reflection of the light on the silicon wafer surface and then increase substantially the solar cell conversion efficiency. In this work, we carried out experiments to optimize double AR coating layer with silicon nitride and silicon oxide for the silicon solar cells. The p-type mono crystalline silicon wafers with $156{\times}156mm^2$ area, 0.5-3 ${\Omega}{\cdot}cm$ resistivity, and $200{\mu}m$ thickness were used. All wafers were textured in KOH solution, doped with $POCl_3$ and removed PSG before ARC process. The optimized thickness of each ARC layer was calculated by theoretical equation. For the double layer of AR coating, silicon nitride layer was deposited first using $SiH_4$ and $NH_3$, and then silicon oxide using $SiH_4$ and $N_2O$. As a result, reflectance of $SiO_2/SiN_x$ layer was lower than single $SiN_x$ and then it resulted in increase of short-circuit current and conversion efficiency. It indicates that the double AR coating layer is necessary to obtain the high efficiency solar cell with PECVD already used in commercial line.