• 한국정밀공학회지
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• 제19권5호
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• 한국정밀공학회지
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• 제22권1호
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• pp.199-206
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• 2005

Mask manufacturing is a high COC and COO process in developing of semiconductor devices because of mask production tool with high resolution. Direct writing has been thought to be the one of the patterning method to cope with development or small-lot production of the device. This study consists two categories. One is the additional process of the direct and maskless patterning generation using SLA for easy and convenient application and the other is a removal process using wet-etching process. In this study, cured status of epoxy pattern is most important parameter because of the beer-lambert law according to the diffusion of UV light. In order to improve the contact force between patterns and substrate, prime process was performed and to remove the semi-cured resin which makes a bad effects to the pattern, spin cleaning process using TPM was also performed. At a removal process, contact force between photo-curable resin as an etching mask and Si wafer is important parameter.

• Design & Manufacturing
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• 제12권1호
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• pp.47-51
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• 2018

As the IT industry rapidly progresses, the functions of electronic devices and display devices are integrated with high density, and the model is changed in a short period of time. To implement the integration technology, a uniform micro-pattern implementation technique to drive and control the product is required. The most important technology for the micro pattern generation is the exposure processing technology. Failure to implement the basic pattern in this process cannot satisfy the demands in the manufacturing field. In addition, the conventional exposure method of the mask method cannot cope with the small-scale production of various types of products, and it is not possible to implement a micro-pattern, so an alternative technology must be secured. In this study, the technology to implement the required micro-pattern in semiconductor processing is presented through the photolithography process and plasma etching.

• 청정기술
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• 제29권4호
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• pp.255-261
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• 2023

파워반도체는 전력의 변환, 변압, 분배 및 전력제어 등을 감당하는데 사용되는 반도체이다. 최근 세계적으로 고전압 파워반도체의 수요는 다양한 산업분야에 걸쳐 증가하고 있는 추세이며 해당 산업에서는 고전압 IGBT 부품의 최적화 연구가 절실한 상황이다. 고전압 IGBT개발을 위해서 wafer의 저항값 설정과 주요 단위공정의 최적화가 완성칩의 전기적특성에 큰 변수가 되며 높은 항복전압(breakdown voltage) 지지를 위한 공정 및 최적화 기술 확보가 중요하다. 식각공정은 포토리소그래피공정에서 마스크회로의 패턴을 wafer에 옮기고, 감광막의 하부에 있는 불필요한부분을 제거하는 공정이고, 이온주입공정은 반도체의 제조공정 중 열확산기술과 더불어 웨이퍼 기판내부로 불순물을 주입하여 일정한 전도성을 갖게 하는 과정이다. 본 연구에서는 IGBT의 3.3 kV 항복전압을 지지하는 ring 구조형성의 중요한 공정인 field ring 식각실험에서 건식식각과 습식식각을 조절해 4가지 조건으로 나누어 분석하고 항복전압확보를 위한 안정적인 바디junction 깊이형성을 최적화하기 위하여 TEG 설계를 기초로 field ring 이온주입공정을 4가지 조건으로 나누어 분석한 결과 식각공정에서 습식 식각 1스텝 방식이 공정 및 작업 효율성 측면에서 유리하며 링패턴 이온주입조건은 도핑농도 9.0E13과 에너지 120 keV로, p-이온주입 조건은 도핑농도 6.5E13과 에너지 80 keV로, p+ 이온주입 조건은 도핑농도 3.0E15와 에너지 160 keV로 최적화할 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.247-250
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• 2006

현재 고밀도 반도체제작 환경에서는 Reactive ion Etching (RIE) 과정에서의 생산성을 극대화하기 위해서 비이상적인 공정장비를 발견하는 것이 매우 중요하다. 생산과정에서 오류발견의 중요성을 설명하기 위해 Support Vector Machine (SVM)은 실시간으로 공정오류에 대한 판단에 대한 도움을 주기 위해 사용되었다. baseline run으로부터 얻은 데이터로 SVM 모델을 구성하고 정상인 run 데이터와 비정상 run 데이터로 SVM 모델을 검증한다. 통계적 공정제어에서 흔히 이용되는 control limits를 도입하여 정상데이터가 내재하고 있는 램덤 변화율이 반영된 SVM 모델 기반의 control limits를 수립하고, 그 control limits를 바탕으로 오류발견을 실행한다. SVM을 이용함으로써 RIE의 오류발견은 run to run 기반에 정상인 run데이터는 0% 오류율이 증명되었다.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.307-312
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• 2014

We present a full finite element analysis for plasma discharge in etching process of semiconductor circuit. The charge transport equations of hydrodynamic diffusion-drift model and the electric field equation were numerically solved in a fully coupled system by using a standard finite element procedure for transient analysis. The proposed method was applied to a real plasma reactor in order to characterize the plasma sheath that is closely related to the yield of the etching process. Throughout the plasma discharge analysis, the base electrode of reactor was tested and modified for improving the uniformity around the wafer edge. The experiment and numerical results were examined along with SEM data of etching quality. The feasibility and usefulness of the proposed method was shown by both numerical and experimental results.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.284-284
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• 2011

Recently, the increasing degree of device integration in the fabrication of Si semiconductor devices, etching processes of nano-scale materials and high aspect-ratio (HAR) structures become more important. Due to this reason, etch selectivity control during etching of HAR contact holes and trenches is very important. In this study, The etch selectivity and etch rate of TEOS oxide layer using ACL (amorphous carbon layer) mask are investigated various process parameters in CH2F2/C4F8/O2/Ar plasma during etching TEOS oxide layer using ArF/BARC/SiOx/ACL multilevel resist (MLR) structures. The deformation and etch characteristics of TEOS oxide layer using ACL hard mask was investigated in a dual-frequency superimposed capacitively coupled plasma (DFS-CCP) etcher by different fHF/ fLF combinations by varying the CH2F2/ C4F8 gas flow ratio plasmas. The etch characteristics were measured by on scanning electron microscopy (SEM) And X-ray photoelectron spectroscopy (XPS) analyses and Fourier transform infrared spectroscopy (FT-IR). A process window for very high selective etching of TEOS oxide using ACL mask could be determined by controlling the process parameters and in turn degree of polymerization. Mechanisms for high etch selectivity will discussed in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• 센서학회지
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• 제20권3호
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• pp.187-192
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• 2011

Abrasive blaster is similar to sand blaster, and effectively removes hard and brittle materials. Exiting abrasive blaster has applied to rough working such as deburring and rough finishing. As the need for machining of ceramics, semiconductor, electronic devices and LCD are increasing, micro abrasive blaster was developed, and became the inevitable technique to micromachining. This paper describes the performance of the micro blaster in MEMS process of glass and succeed in domestically producing complete micro blaster. Diameter of hole and width of line in this etching is 100 ${\mu}m$ ~ 1000 ${\mu}m$. Experimental results showed good performance in micro channel and hole in glass wafer. Therefore, this micro blaster could be effectively applied to the micro machining of semiconductor, micro PCR chip.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.173-179
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• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.