• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.2074-2076
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• 2000

In this paper, RFICP equipment is designed and manufactured with the aid of high frequency discharge to produce uniform plasma with high density and large diameter. And $SF_6$ gas is used to investigate plasma characteristics. The electron density and temperature, potential dependence of $SF_6$ plasma in accordance with its operating pressure, gas flux and input power are measured by the method of Langmuir probe. The etching characteristics of the plasma is researched in accordance with operating pressure, gas flux, input power to apply to Silicon Wafer which is used in the field of semiconductor process. The proposed RFICP equipment, in this paper, has relatively excellent etching characteristics, and is thought to be element of oxidization-sheath etching facility in semiconductor manufacturing process.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 센서학회지
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• 제7권1호
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• pp.73-82
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• 1998

실리콘 표면 미세가공에 있어서, 새로 개발된 HF 기상식각 공정은 미소구조체들을 띄우는데 매우 효과적임을 입증하였다. 무수 불화수소와 메탄올을 이용한 기상식각 시스템에 대한 기능 및 특성을 기술하였고, 실리콘 미세구조체룰 띄우기 위한 회생층 산화막들의 선택적 식각특성이 고찰되었다. 구조체층으로는 인이 주입된 다결정실리콘이나 SOI 기판의 단결정실리콘을 사용하였다. 회생층으로는 TEOS 산화막, 열산화막, 저온산화막을 사용하였다. 기존 습식식각과 비교해 볼 때, 공정에 기인된 고착현강이나 잔류물질이 없는 미세구조체를 성공적으로 제작하였다.

• Journal of information and communication convergence engineering
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• 제10권3호
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• pp.295-299
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• 2012

Defect generation during organic bottom anti-reflective coating (BARC) in the photo lithography process is closely related to humidity control in the BARC coating unit. Defects are related to the water component due to the humidity and act as a blocking material for the etching process, resulting in an extreme pattern bridging in the subsequent BARC etching process of the poly etch step. In this paper, the lower limit for the humidity that should be stringently controlled for to prevent defect generation during BARC coating is proposed. Various images of defects are inspected using various inspection tools utilizing optical and electron beams. The mechanism for defect generation only in the specific BARC coating step is analyzed and explained. The BARC defect-induced gate pattern bridging mechanism in the lithography process is also well explained in this paper.

• Journal of information and communication convergence engineering
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• 제5권3호
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• pp.215-218
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• 2007

In this paper, amorphous semiconductor and insulator thin film are etched using reactive ion etcher. At that time, we experiment in various RIE conditions (chamber pressure, gas flow rate, rf power, temperature) that have effects on quality of thin film. The using gases are $CF_4,\;CF_4+O_2,\;CCl_2F_2,\;CHF_3$ gases. The etching of a-Si:H thin film use $CF_4,\;CF_4+O_2$ gases and the etching of $a-SiO_2,\;a-SiN_x$ thin film use $CCl_2F_2,\;CHF_3$ gases. The $CCl_2F_2$ gas is particularly excellent because the selectivity of between a-Si:H thin film and $a-SiN_x$ thin film is 6:1. We made precise condition on dry etching with uniformity of 5%. If this dry etching condition is used, that process can acquire high yield and can cut down process cost.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.119-124
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• 2023

In this study, experimental approach of the measurement of condensation and evaporation heat transfer coefficients is discussed for mixed refrigerants using in the ultra low-temperature cooling system for semiconductor etching process. An experimental apparatus was described performing the condensation and evaporation heat transfer measurements for mixed refrigerants. The mixed refrigerant used in this study was composed of the optimal mixture determined in previous research, with a composition of Ar:R14:R23:R218 = 0.15:0.4:0.15:0.3. The experiments were conducted over a temperature range from -82℃ to 15℃ and at pressures ranging from 18.5 bar to 5 bar. The convection heat transfer coefficients of the mixed refrigerant were measured at flow rates corresponding to actual operating conditions. The condensation heat transfer coefficient ranged from approximately 0.7 to 0.9 kW/m2K, while the evaporation heat transfer coefficient ranged from 1.0 to 1.7 kW/m2K. The detailed discussion of the experimental methods, procedures, and results were described in this paper.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.16-19
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• 2017

For the economical and environmental-friendly fabrication of polisher, Mo mask layer were sputtered on glass substrate instead of Cr mask material. Mo mask layers were sputtered by pulsed-DC sputtering and Photoresist patterns were formed on Mo mask layer for different develop times and optimized. After Mo mask layer were patterned and exposed glass was wet etched by HF solution for different etching times, the remaining Mo mask was stripped by using Al etchant. Develop time of 30 sec and HF wet etching time of 3 min were selected as optimized process condition and applied to the fabrication of polisher.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.1485-1488
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• 1997

The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.