• Title/Summary/Keyword: Semiconductor etching process

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Dry Etching of GaAs and AlgaAs Semiconductor Materials in High Density BCl$_3$, BCl$_3$/Ar Inductively Coupled Plasmas (BCl$_3$, BCl$_3$/Ar 고밀도 유도결합 플라즈마를 이용한 GaAs 와 AlGaAs 반도체 소자의 건식식각)

  • Lim, Wan-Tae;Baek, In-Kyoo;Lee, Je-Won;Cho, Guan-Sik;Jeon, Min-Hyun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.31-36
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    • 2003
  • We investigated dry etching of GaAs and AlGaAs in a high density planar inductively coupled plasma system with $BCl_3$ and $BCl_3/Ar$ gas chemistry. A detailed process study as a function of ICP source power, RIE chuck power and $BCl_3/Ar$ mixing ratio was performed. At this time, chamber pressure was fixed at 7.5 mTorr. The ICP source power and RIE chuck power were varied from 0 to 500 W and from 0 to 150 W, respectively. GaAs etch rate increased with the increase of ICP source power and RE chuck power. It was also found that etch rate of GaAs in $BCl_3$ gas with 25% Ar addition was superior to that of GaAs in a pure $BCl_3$ (20 sccm $BCl_3$) plasma. The result was same with AlGaAs. We expect that high ion-assisted effect in $BCl_3$/Ar plasma increased etch rates of both materials. The GaAs and AIGaAs features etched at 20 sccm $BCl_3$ and $15BCl_3/5Ar$ with 300 W ICP source power, 100 W RIE chuck power and 7.5 mTorr showed very smooth surfaces(RMS roughness < 2 nm) and excellent sidewall. XPS study on the surfaces of processed GaAs also proved extremely clean surfaces of the materials after dry etching.

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A Chemically-driven Top-down Approach for the Formation of High Quality GaN Nanostructure with a Sharp Tip

  • Kim, Je-Hyeong;O, Chung-Seok;Go, Yeong-Ho;Go, Seok-Min;Jo, Yong-Hun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.48-48
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    • 2011
  • We have developed a chemically-driven top-down approach using vapor phase HCl to form various GaN nanostructures and successfully demonstrated dislocation-free and strain-relaxed GaN nanostructures without etching damage formed by a selective dissociation method. Our approach overcomes many limitations encountered in previous approaches. There is no need to make a pattern, complicated process, and expensive equipment, but it produces a high-quality nanostructure over a large area at low cost. As far as we know, this is the first time that various types of high-quality GaN nanostructures, such as dot, cone, and rod, could be formed by a chemical method without the use of a mask or pattern, especially on the Ga-polar GaN. It is well known that the Ga-polar GaN is difficult to etch by the common chemical wet etching method because of the chemical stability of GaN. Our chemically driven GaN nanostructures show excellent structure and optical properties. The formed nanostructure had various facets depending on the etching conditions and showed a high crystal quality due to the removal of defects, such as dislocations. These structure properties derived excellent optical performance of the GaN nanostructure. The GaN nanostructure had increased internal and external quantum efficiency due to increased light extraction, reduced strain, and improved crystal quality. The chemically driven GaN nanostructure shows promise in applications such as efficient light-emitting diodes, field emitters, and sensors.

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Endpoint Detection Using Hybrid Algorithm of PLS and SVM (PLS와 SVM복합 알고리즘을 이용한 식각 종료점 검출)

  • Lee, Yun-Keun;Han, Yi-Seul;Hong, Sang-Jeen;Han, Seung-Soo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.9
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    • pp.701-709
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    • 2011
  • In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.

Optical In-Situ Plasma Process Monitoring Technique for Detection of Abnormal Plasma Discharge

  • Hong, Sang Jeen;Ahn, Jong Hwan;Park, Won Taek;May, Gary S.
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.2
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    • pp.71-77
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    • 2013
  • Advanced semiconductor manufacturing technology requires methods to maximize tool efficiency and improve product quality by reducing process variability. Real-time plasma process monitoring and diagnosis have become crucial for fault detection and classification (FDC) and advanced process control (APC). Additional sensors may increase the accuracy of detection of process anomalies, and optical monitoring methods are non-invasive. In this paper, we propose the use of a chromatic data acquisition system for real-time in-situ plasma process monitoring called the Plasma Eyes Chromatic System (PECS). The proposed system was initially tested in a six-inch research tool, and it was then further evaluated for its potential to detect process anomalies in an eight-inch production tool for etching blanket oxide films. Chromatic representation of the PECS output shows a clear correlation with small changes in process parameters, such as RF power, pressure, and gas flow. We also present how the PECS may be adapted as an in-situ plasma arc detector. The proposed system can provide useful indications of a faulty process in a timely and non-invasive manner for successful run-to-run (R2R) control and FDC.

Fabrication of Si Nano Dots by Using Diblock Copolymer Thin Film (블록 공중합체 박막을 이용한 실리콘 나노점의 형성)

  • Kang, Gil-Bum;Kim, Seong-Il;Kim, Young-Hwan;Park, Min-Chul;Kim, Yong-Tae;Lee, Chang-Woo
    • Journal of the Microelectronics and Packaging Society
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    • v.14 no.2 s.43
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    • pp.17-21
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    • 2007
  • Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

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Optimization of Glass Wafer Dicing Process using Sand Blast (Sand Blast를 이용한 Glass Wafer 절단 가공 최적화)

  • Seo, Won;Koo, Young-Mo;Ko, Jae-Woong;Kim, Gu-Sung
    • Journal of the Korean Ceramic Society
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    • v.46 no.1
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    • pp.30-34
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    • 2009
  • A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

Comparative Study of Uniform and Nonuniform Grating Couplers for Optimized Fiber Coupling to Silicon Waveguides

  • Lee, Moon Hyeok;Jo, Jae Young;Kim, Dong Wook;Kim, Yudeuk;Kim, Kyong Hon
    • Journal of the Optical Society of Korea
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    • v.20 no.2
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    • pp.291-299
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    • 2016
  • We have investigated the ultimate limits of nonuniform grating couplers (NGCs) for optimized fiber coupling to silicon waveguides, compared to uniform grating couplers (UGCs). Simple grating coupler schemes, which can be fabricated in etching steps of the conventional complementary metal-oxide semiconductor (CMOS) process on silicon-on-insulator (SOI) wafers without forming any additional overlay structure, have been simulated numerically and demonstrated experimentally. Optimum values of the grating period, fill factor, and groove number for ultimate coupling efficiency of the NGCs are determined from finite-difference time-domain (FDTD) simulation, and confirmed with experimentally demonstrated devices by comparison to those for the UGCs. Our simulated results indicate that maximum coupling efficiency of NGCs is possible when the minimum pattern size is below 50 nm, but the experimental value for the maximum coupling efficiency is limited by the attainable fabrication tolerance in a practical device process.

Studies on the Morphology of the CVD Tungsten Film (기상화학증착 텅스텐 막질의 표면 형태에 관한 연구)

  • Jeon, Dong-Soo;Kim, Sun-Rae;Lee, Sung-Young;Park, Young-Kyou;Jeon, Young-Soo
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.377-378
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    • 2008
  • Morphology is one of important issues when developing a layer of CVD-W. we need to control the process more precisely that is filling gaps between BL(bit line)and DC(direct contact). Whereas we are facing to difficulties like not-filling contacts due to marginal problems in deposition and etching process. This paper is for investigating a method to resolve morphology problem with strengthening the condition of seasoning.

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Treatment of Waste Dry Etching Gas in Semiconductors Manufacturing Process

  • Yamamoto, Hideki;Kawahara, Takahiro;Shibata, Junji
    • Proceedings of the IEEK Conference
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    • 2001.10a
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    • pp.711-714
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    • 2001
  • A new technology to make fluoride gas such as NF$_3$contained in the exhaust gas from semiconductor manufacturing plants convert directly into a harmless substance have been established and new concept on the disposal treatment of global warming gases were presented. Experimental results verify that the chemical reactions can be take place at substantially lower temperature of 80-40$0^{\circ}C$ as compared with the combustion treatment method. Reaction product is mainly metal fluoride which is a harmless and a valuable chemical material as one of new resources. The other favorable characteristics are that the continuous treatment is possible at a low temperature under atmospheric pressure. Furthermore this process is compact, easily controllable and safely operable at low running cost. This paper concerns with a new harmless disposal treatment of toxic global warming gas.

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Fabrication of BLT Nanotubes for 3D Nanotube Capacitor (3D Nanotube Capacitor 구현을 위한 BLT Nanotube 제작)

  • Seo, Bo-Ik;Shaislamov Ulugbek;Kim, Sang-Woo;Hong, Seok-Kyung;Yang, Bee-Lyong
    • Journal of the Korean Ceramic Society
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    • v.43 no.4 s.287
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    • pp.220-223
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    • 2006
  • BLT nanotubes were synthesized by using simple and convenient method template-wetting process. Porous alumina membranes were prepared by 2 step anodic oxidation as the template. To improve wetting properties and make low surface energy, BLT solution was mixed with polymer. Polymer was removed completely during annealing. After completely etching the template in 30 wt% KOH solution, we demonstrate that BLT nanotubes with a diameter of 200 nm can be fabricated. Grain growth process of BLT nanotubes during baking, and furnace annealing was examined by FE-SEM and XRD.