• Title/Summary/Keyword: Semiconductor Process Data

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The diagnosis of Plasma Through RGB Data Using Rough Set Theory

  • Lim, Woo-Yup;Park, Soo-Kyong;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.413-413
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    • 2010
  • In semiconductor manufacturing field, all equipments have various sensors to diagnosis the situations of processes. For increasing the accuracy of diagnosis, hundreds of sensors are emplyed. As sensors provide millions of data, the process diagnosis from them are unrealistic. Besides, in some cases, the results from some data which have same conditions are different. We want to find some information, such as data and knowledge, from the data. Nowadays, fault detection and classification (FDC) has been concerned to increasing the yield. Certain faults and no-faults can be classified by various FDC tools. The uncertainty in semiconductor manufacturing, no-faulty in faulty and faulty in no-faulty, has been caused the productivity to decreased. From the uncertainty, the rough set theory is a viable approach for extraction of meaningful knowledge and making predictions. Reduction of data sets, finding hidden data patterns, and generation of decision rules contrasts other approaches such as regression analysis and neural networks. In this research, a RGB sensor was used for diagnosis plasma instead of optical emission spectroscopy (OES). RGB data has just three variables (red, green and blue), while OES data has thousands of variables. RGB data, however, is difficult to analyze by human's eyes. Same outputs in a variable show different outcomes. In other words, RGB data includes the uncertainty. In this research, by rough set theory, decision rules were generated. In decision rules, we could find the hidden data patterns from the uncertainty. RGB sensor can diagnosis the change of plasma condition as over 90% accuracy by the rough set theory. Although we only present a preliminary research result, in this paper, we will continuously develop uncertainty problem solving data mining algorithm for the application of semiconductor process diagnosis.

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Effect of Process Parameters on Surface Roughness in Lapping Operation (래핑의 공정변수가 표면거칠기에 미치는 영향)

  • Choi, Mansung
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.4
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    • pp.9-13
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    • 2013
  • Lapping is a very complicated and random process resulting from the variation of abrasive grains in its sizes and shapes and from the numerous factors having an effect on the process quality. This paper presents a study of a $2^4$ full factorial experimental design and analysis to optimize surface quality in lapping operation. The optimization of the factors to obtain minimum surface roughness was carried out by incorporating effect plots, main effect plots, interaction plots, analysis of variance(ANOVA), surface plots, and contour plots. The statistical design experiments, designed to reduce the total number of experiments required, indicated that, within the selected conditions, all the parameters influenced at a significance level of 5%. In addition, some of the possible interactions between these parameters also influenced the lapping process, especially those that were of third order. A regression model was suggested and fitted the experimental data very well.

FPGA Design of a Parallel Canny Edge Detector with Optimized Local Buffers (로컬 버퍼 최적화를 통한 병렬 처리 캐니 경계선 검출기의 FPGA 설계)

  • Ingi Min;Suhyun Sim;Seungwon Hwang;Sunhee Kim
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.59-65
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    • 2023
  • Edge detection in image processing and computer vision is one of the most fundamental operations. Canny edge detection algorithm has excellent performance and is currently widely used. However, it is difficult to process the algorithm in real-time because the algorithm is complex. In this study, the equations required in the algorithm were simplified to facilitate hardware implementation, and the calculation speed was increased by using a parallel structure. In particular, the size and management of local buffers were selected in consideration of parallel processing and filter size so that data could be processed without bottlenecks. It was designed in verilog and implemented in FPGA to verify operation and performance.

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Performance Comparison of LSTM-Based Groundwater Level Prediction Model Using Savitzky-Golay Filter and Differential Method (Savitzky-Golay 필터와 미분을 활용한 LSTM 기반 지하수 수위 예측 모델의 성능 비교)

  • Keun-San Song;Young-Jin Song
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.3
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    • pp.84-89
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    • 2023
  • In water resource management, data prediction is performed using artificial intelligence, and companies, governments, and institutions continue to attempt to efficiently manage resources through this. LSTM is a model specialized for processing time series data, which can identify data patterns that change over time and has been attempted to predict groundwater level data. However, groundwater level data can cause sen-sor errors, missing values, or outliers, and these problems can degrade the performance of the LSTM model, and there is a need to improve data quality by processing them in the pretreatment stage. Therefore, in pre-dicting groundwater data, we will compare the LSTM model with the MSE and the model after normaliza-tion through distribution, and discuss the important process of analysis and data preprocessing according to the comparison results and changes in the results.

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Design of Process Management System based on Data Mining and Artificial Modelling for the Etching Process (데이터 마이닝과 지능 모델링에 기반한 에칭공정의 공정관리시스템 설계)

  • Bae, Hyeon;Kim, Sung-shin;Woo, Kwang-Bang
    • Journal of the Korean Institute of Intelligent Systems
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    • v.14 no.4
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    • pp.390-395
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    • 2004
  • A semiconductor manufacturing process is the complicate and dynamic process, and consists of many sub-processes. An etching process is the most important process in the semiconductor fabrication. In this paper, the decision support system based upon data mining and knowledge discovery is an important factor to improve the productivity and yield. The proposed decision support system consists of a neural network model and an inference system based on fuzzy logic Firstly, the product results are predicted by the neural network model constructed by the product patterns that represent the quality of the etching process. And the product patters are classified by expert's knowledge. Finally, the product conditions are estimated by the fuzzy inference system using the rules extracted from the classified patterns. Prediction of product qualities can be linked to each input and process variables. We employ data mining and intelligent techniques to find the best condition of the etching process. The proposed decision support system is efficient and easy to be implemented for the process management based upon expert's knowledge.

Adaptive Smoothing Algorithm Based on Censoring for Removing False Color Noise Caused by De-mosaicing on Bayer Pattern CFA (Bayer 패턴의 de-mosaicing 과정에서 발생하는 색상잡음 제거를 위한 검열기반 적응적 평탄화 기법)

  • Hwang, Sung-Hyun;Kim, Chae-Sung;Moon, Ji-He
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.403-406
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    • 2005
  • The purpose of this paper is to propose ways to remove false color noise (FCN) generated during de-mosaicing on RGB Bayer pattern images. In case of images sensors adapting Bayer pattern color filters array (CFA), de-mosaicing is conducted to recover the RGB color data in single pixels. Here, FCN phenomena would occur where there is clearer silhouette or contrast of colors. The FCN phenomena found during de-mosaicking process appears locally in the edges inside the image and the proposed method of eliminating this is to convert RGB color space to YCbCr space to conduct smoothing process. Moreover, for edges where different colors come together, censoring based smoothing technique is proposed as a way to minimize color blurring effect.

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Die Shift Measurement of 300mm Large Diameter Wafer (300mm 대구경 웨이퍼의 다이 시프트 측정)

  • Lee, Jae-Hyang;Lee, Hye-Jin;Park, Sung-Jun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.708-714
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    • 2016
  • In today's semiconductor industry, manufacturing technology is being developed for the purpose of processing large amounts of data and improving the speed of data processing. The packaging process in semiconductor manufacturing is utilized for the purpose of protecting the chips from the external environment and supplying electric power between the terminals. Nowadays, the WLP (Wafer-Level Packaging) process is mainly used in semiconductor manufacturing because of its high productivity. All of the silicon dies on the wafer are subjected to a high pressure and temperature during the molding process, so that die shift and warpage inevitably occur. This phenomenon deteriorates the positioning accuracy in the subsequent re-distribution layer (RDL) process. In this study, in order to minimize the die shift, a vision inspection system is developed to collect the die shift measurement data.

Structure and Electrical Properties of SiGe HBTs Designed with Bottom Collector and Single Metal Contact (Bottom Collector와 단일 금속층 구조로 설계된 SiGe HBT의 전기적 특성)

  • Choi, A.R.;Choi, S.S.;Yun, S.N.;Kim, S.H.;Seo, H.K.;Shim, K.H.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.187-187
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    • 2007
  • This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence (< $200^{\circ}C$) on electrical properties. The feasible application in 1~2GHz frequency from measured data $BV_{CEO}$ ~10V, $f_r$~14 GHz, ${\beta\simeq}110$, NF~1 dB using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

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Possibility of Spreading Infectious Diseases by Droplets Generated from Semiconductor Fabrication Process (반도체 FAB의 비말에 의한 감염병 전파 가능성 연구)

  • Oh, Kun-Hwan;Kim, Ki-Youn
    • Journal of Korean Society of Occupational and Environmental Hygiene
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    • v.32 no.2
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    • pp.111-115
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    • 2022
  • Objectives: The purpose of this study is to verify whether droplet-induced propagation, the main route of infectious diseases such as COVID-19, can occur in semiconductor FAB (Fabrication), based on research results on general droplet propagation. Methods: Through data surveys droplet propagation was modeled through simulation and experimental case analysis according to general (without mask) and mask-wearing conditions, and the risk of droplet propagation was inferred by reflecting semiconductor FAB operation conditions (air current, air conditioning system, humidity, filter conditions). Results: Based on the results investigated to predict the possibility of spreading infectious diseases in semiconductor FAB, the total amount of droplet propagation (concentration), propagation distance, and virus life in FAB were inferred by reflecting the management parameter of semiconductor FAB. Conclusions: The total amount(concentration) of droplet propagation in the semiconductor fab is most affected by the presence or absence of wearing a mask and the line air dilution rate has some influence. when worn it spreads within 0.35~1m, and since the humidity is constant the virus can survive in the air for up to 3 hours. as a result the semiconductor fab is judged to be and effective space to block virus propagation due to the special environmental condition of a clean room.

Online Experts Screening the Worst Slicing Machine to Control Wafer Yield via the Analytic Hierarchy Process

  • Lin, Chin-Tsai;Chang, Che-Wei;Wu, Cheng-Ru;Chen, Huang-Chu
    • International Journal of Quality Innovation
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    • v.7 no.2
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    • pp.141-156
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    • 2006
  • This study describes a novel algorithm for optimizing the quality yield of silicon wafer slicing. 12 inch wafer slicing is the most difficult in terms of semiconductor manufacturing yield. As silicon wafer slicing directly impacts production costs, semiconductor manufacturers are especially concerned with increasing and maintaining the yield, as well as identifying why yields decline. The criteria for establishing the proposed algorithm are derived from a literature review and interviews with a group of experts in semiconductor manufacturing. The modified Delphi method is then adopted to analyze those results. The proposed algorithm also incorporates the analytic hierarchy process (AHP) to determine the weights of evaluation. Additionally, the proposed algorithm can select the evaluation outcomes to identify the worst machine of precision. Finally, results of the exponential weighted moving average (EWMA) control chart demonstrate the feasibility of the proposed AHP-based algorithm in effectively selecting the evaluation outcomes and evaluating the precision of the worst performing machines. So, through collect data (the quality and quantity) to judge the result by AHP, it is the key to help the engineer can find out the manufacturing process yield quickly effectively.