• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.14-22
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• 2023

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.12
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• pp.230-238
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• 1999

This paper describes a research work of developing computer-aided design of lead frame, semiconductor, with blanking operation which is very precise for progressive working. Approach to the system is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. This system has been written in AutoLISP on the AutoCAD using a personal computer and in I-DEAS Drafting Programming Language on the I-DEAS Master Series Drafting with Workstation, HP9000/715(64) and tool kit on the ESPRIT. Transference of data among AutoCAD, I-DEAS Master Series Drafting, and ESPRIT is accomplished by DXF(drawing exchange format) and IGES(initial graphics exchange specification) methods. This system is composed of six modules, which are input and shape treatment, production feasibility check, strip-layout, die-layout, modelling, and post-processor modules. The system can design process planning and Die design considering several factors and generate NC data automatically according to drawings of die-layout module. As forming process of high precision product and die design system using 2-D geometry recognition are integrated with technology of process planning, die design, and CAE analysis, standardization of die part in die design and process planning of high pression product for semiconductor lead frame is possible to set. Results carried out in each module will provide efficiencies to the designer and the manufacturer of lead frame, semiconductor.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.804-809
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• 2013

The current state monitoring system at a semiconductor manufacturing process is based on the manually collected sensor data, which involves limitations when it comes to complex malfunction detection and real time monitoring. This study aims to design a situation recognition algorithm to form a network over time by creating a domain ontology and to suggest a system to provide users with services by generating events upon finding risk factors in the semiconductor process. To this end, a multiple sensor node for situational inference was designed and tested. As a result of the experiment, events to which the rule of time inference was applied occurred for the contents formed over time with regard to a quantity of collected data while the events that occurred with regard to malfunction and external time factors provided log data only.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.161-166
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• 2021

Errors in the semiconductor process are generated by a change in the state of the equipment, and errors usually arise when the state of the equipment changes or when parts that make up the equipment have flaws. In this investigation, we anticipated that aging of the mass flow controller in the plasma enhanced chemical vapor deposition SiO2 thin film deposition method caused a minute flow rate shift. In seven cases, fourier transformation infrared film quality analysis of the deposited thin film was used to characterize normal and pathological processes. The plasma condition was monitored using optical emission spectrometry data as the flow rate changed during the procedure. Preprocessing was used to apply the collected OES data to the artificial immune system algorithm, which was then used to process diagnosis. Through comparisons between datasets, the learning algorithm compared classification accuracy and improved the method. It has been confirmed that data characterized as a normal process and abnormal processes with differing flow rates may be discriminated by themselves using the artificial immune system data mining method.

• Journal of the Korea Safety Management & Science
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• v.23 no.3
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• pp.27-33
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• 2021

The purpose of this study is to present a novel indicator for analyzing machine failure based on its idle time and productivity. Existing machine repair plan was limited to machine experts from its manufacturing industries. This study evaluates the repair status of machines and extracts machines that need improvement. In this study, F-RPN was calculated using the etching process data provided by the 2018 PHM Data Challenge. Each S(S: Severity), O(O: Occurence), D(D: Detection) is divided into the idle time of the machine, the number of fault data, and the failure rate, respectively. The repair status of machine is quantified through the F-RPN calculated by multiplying S, O, and D. This study conducts a case study of machine in a semiconductor etching process. The process capability index has the disadvantage of not being able to divide the values outside the range. The performance of this index declines when the manufacturing process is under control, hereby introducing F-RPN to evaluate machine status that are difficult to distinguish by process capability index.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.1
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• pp.113-122
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• 1996

As integrity of semiconductor device is increased, accurate and efficient modeling and recipe generation of semiconductor fabrication procsses are necessary. Among the major semiconductor manufacturing processes, dry etc- hing process using gas plasma and accelerated ion is widely used. The process involves a variety of the chemical and physical effects of gas and accelerated ions. Despite the increased popularity, the complex internal characteristics made efficient modeling difficult. Because of difficulty to determine the control input for the desired output, the recipe generation depends largely on experiences of the experts with several trial and error presently. In this paper, the optimal control of the etching is carried out in the following two phases. First, the optimal neural network models for etching process are developed with genetic algorithm utilizing the input and output data obtained by experiments. In the second phase, search for optimal control inputs in performed by means of using the optimal neural network developed together with genetic algorithm. The results of study indicate that the predictive capabilities of the neural network models are superior to that of the statistical models which have been widely utilized in the semiconductor factory lines. Search for optimal control inputs using genetic algorithm is proved to be efficient by experiments. (author). refs., figs., tabs.

• Journal of the Korean Data and Information Science Society
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• v.18 no.3
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• pp.773-782
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• 2007

The statistical process control charts are very extensively used for monitoring of process mean, deviation, defect rate or reject rate. In this paper we consider a control chart to monitor the process reject rate in the high yield process, which is based on the observed cumulative probability of the number of items inspected until r defective items are observed. We first propose selection of the optimal value of r in the CPC-r charts, and also consider the usefulness of the chart in high yield process such as semiconductor or TFT-LCD manufacturing process.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.401-406
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• 1988

Various types and huge volume of information such as process instructions, work-in process and parametric data are created in a wafer fabrication process and should be provided to personnels inside or outside the facility. This article describes design criteria and functional description on the information system for small-scale wafer fabrication process to accomplish paperless fab and to support efficient fab management.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.174-178
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• 2007

The cleaning process to remove small particles, ions, and other polluted sources is one of the major parts in the recent semiconductor industry because it can cause fatal errors on the quality of the final products. According to the other reports, the major factors of bath's fluid motion are the cleaning method, nozzle, the geometry (of bath, guide and wafer), and the position (of guide and wafer). So to enhance cleaning efficiency in the bath, these factors must be controlled. The purpose of this study is to analyze and visualize fluid motion in the cleaning bath as basic data for designing the nozzle system and finding the process control parameters. For that, we used the general CFD code FLUENT.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.