• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 대한전자공학회논문지
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• 제23권6호
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• pp.923-928
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• 1986

This paper describes the design and fabrication of a high performance digital tuning analog component integrated circuit that contains a television station detector and decoders(H and L types). When the comparator level sampling method is used, this integrated circuit can be used as a stable channel selector for an external circuit with very large signal variation. It has been fabricated using the SST bipolar standard process and its chip size is 2.2x2.1mm\ulcorner As a result, we have succeeded in fabricating the IC that satisfies the D.C characteristics, and the channel station detector and decoder function.

• 산업경영시스템학회지
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• 제45권4호
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• pp.86-98
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• 2022

Recently, many studies have been conducted to improve quality by applying machine learning models to semiconductor manufacturing process data. However, in the semiconductor manufacturing process, the ratio of good products is much higher than that of defective products, so the problem of data imbalance is serious in terms of machine learning. In addition, since the number of features of data used in machine learning is very large, it is very important to perform machine learning by extracting only important features from among them to increase accuracy and utilization. This study proposes an anomaly detection methodology that can learn excellently despite data imbalance and high-dimensional characteristics of semiconductor process data. The anomaly detection methodology applies the LIME algorithm after applying the SMOTE method and the RFECV method. The proposed methodology analyzes the classification result of the anomaly classification model, detects the cause of the anomaly, and derives a semiconductor process requiring action. The proposed methodology confirmed applicability and feasibility through application of cases.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.68-74
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• 2017

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Up to now there have been a lot of researches on thermal NIL, but most of them have been focused on polymer deformation in the molding process and there are very few studies on the cooling and demolding process. In this paper a cooling process of the polymer resist in thermal NIL is analyzed with finite element method. The modeling of cooling process for mold, polymer resist and substrate is developed. And the cooling process is numerically investigated with the effects of imprinting temperature and residual layer thickness of polymer resist on stress distribution of the polymer resist. The results show that the lower imprinting temperature, the higher the maximum von Mises stress and that the thicker the residual layer, the greater maximum von Mises stress.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• 전기학회논문지
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• 제61권9호
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• pp.1330-1335
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• 2012

This paper proposes an automatic measurement sampling method for the semiconductor manufacturing process. The method recommends sampling rates using information of process capability indexes and production scheduling plan within the restricted metrology capacity. In addition, it automatically controls the measurement WIP (Work In Process) using measurement priority values to minimize the measurement risks and optimize the measurement capacity. The proposed sampling method minimizes measurement controls in the semiconductor manufacturing process and improves the fabrication productivity via reducing measurement TAT (Turn Around Time), while guaranteeing the level of process quality.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.53-58
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• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.6-11
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• 2011

반도체 및 LCD 세정공정에 사용된 오존수 속의 용해오존을 분해할 수 있는 시스템을 개발함으로써 향후 고성능-저가격의 반도체, LCD PR 박리 및 세정 공정에 적용할 수 있는 핵심 공정기술을 확보하였다. 이 기술을 적용하면 반도체 웨이퍼 및 LCD 평판의 PR 박리 세정 공정을 보다 빠르고 저렴한 비용으로 수행할 수 있으므로 반도체 및 LCD 공정 생산성의 향상을 꾀할 수 있다.

• 반도체디스플레이기술학회지
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• 제6권4호
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• pp.49-52
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• 2007

As the minimum feature size decrease, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT. Charged monodisperse particles are generated using SMPS (Scanning Mobility Particle Sizer) and deposited on the wafer by electrostatic force. The Experimental results agreed with the simulation results well. We calculate the particles loss in pipe flow theoretically and compare with the experimental results.