• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.25-30
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• 2009

We have developed recycling technology of ethylen carbonate to use in photoresist stripping and cleaning process, which will be core processing technology for high performance and low price semiconductor and LCD fabrication. Using this technology, it is possible for semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• IE interfaces
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• v.21 no.2
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• pp.151-160
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• 2008

Defect size distribution is a probability density function for the defects that occur on wafers or glasses during semiconductor/LCD fabrication. It is one of the most important information to estimate manufacturing yield using well-known statistical estimation methods. The defects are detected by automatic optical inspection (AOI) facilities. However, the data that is provided from AOI is not accurate due to resolution of AOI and its defect detection mechanism. It causes distortion of defect size distribution and results in wrong estimation of the manufacturing yield. In this paper, I suggest a size conversion method and a maximum likelihood estimator to overcome the vague defect size information of AOI. The methods are verified by the Monte Carlo simulation that is constructed as similar as real situation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.328-331
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• 1988

Sealed Interface Local Oxidation (SILO) technology has been investigated using a nitride/oxide/nitride three-layered sandwich structure. P-type silicon substrate was either nitrided by rapid thermal processing, or silicon nitride was deposited by LPCVD method. A three-layered sandwich structure was patterned either by reactive ion etch (RIE) mode or by plasma mode. Sacrificial oxidation conditions were also varied. Physical characterization such as cross-section analysis of field oxide, and electrical characterization such as gate oxide integrity, junction leakage and transistor behavior were carried out. It was found that bird's beak was nearly zero or below 0.1um, and the junction leakages in plasma mode were low compared to devices of the same geometry patterned in RIE mode, and gate oxide integrity and transistor behavior were comparable. Conclusively, SILO process is compatible with conventional local oxidation process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1056-1060
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• 2005

We investigated the fabrication and characteristics of the nitride-based spin-polarized LEDs with room-temperature ferromagnetic (Ga,Mn)N layer as a spin injection source. The (Ga,Mn)N thin films having room-temperature ferromagnetic ordering were found to exhibit the negative MR and anomalous Hall resistance up to room temperature, revealing the existence of spin-polarized electrons in (Ga,Mn)N films at room temperature. The electrical characteristics in the spin LEDs did not degraded in spite of the insertion of the (Ga,Mn)N layer into the LED structure. In EL spectra of the spin LEDs, it is confirmed that the devices produce intense EL emission at 7 K as well as room temperature. These results are expected to open up new opportunities to realize room-temperature operating semiconductor spintronic devices.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2189-2191
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• 1999

To improve the reliability of the klystron-modulator systems, the stable operations of the thyratron an important factor of the system are required. The thyratron always has a possibility of self-fire according to the conditions of the applied high voltage and this induces the system fault. Therefore a command charging method was introduced to reduce the applied tim8 of the high voltage into the thyratron. The high voltage switch used in the command charging method is the SCR (1.6 kV, 50A) and consists of 10 SCRs in series to discharge 10 kV. A pulse transformer was used to apply the trigger pulse. The objectives of this research are the fabrication of the semiconductor switch and the study of the experimental result of the operation characteristics of the high voltage semiconductor switch.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.68-72
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• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.59-65
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• 2002

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. Project executed that use conveyor in bay semiconductor A line. But conveyor capability is lacking and rundown happened in equipment. Do design without normal simulation and conveyor system failed. The comparison is peformed through simulation using .AutoMod a window 98 based discrete system simulation software, as a tool for comparing performance of proposed layouts. In this research estimate optimum conveyor capability, there is the purpose.

• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.93-98
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• 2013

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. To successfully imprint a nanosized pattern with the thermal NIL, the process conditions such as temperature and pressure should be appropriately selected. This starts with a clear understanding of polymer material behavior during the thermal NIL process. In this paper, a filling process of the polymer resist into nanometer scale cavities during the thermal NIL at the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer. In the simulation, the filling process and the residual layer formation are numerically investigated. And the effects of pressure and temperature on NIL process, specially the residual layer formation are discussed.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.158-159
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• 2002

스핀 밸브에서는 NiFe, CoFe, Cu등 주요 금속들이 면심입방체(111)로 배향이 용이하지만, 자기 터널 접합 소자에서는 $Al_2$O$_3$ 장벽층이 비정질로서 상부 강자성 전극이 충분히 (111) 배향을 할 수 없기 때문에 top bias 방식의 사용이 거의 불가능하며, bottom bias의 경우에도 교환 바이어스의 크기는 상대적으로 작다[1]. 이를 극복하기 위해 인공 초격자를 이용한 인공 반강자성층(synthetic antiferromagnet - SAF)을 이용하여 높은 교환 바이어스 효과를 구현하고자 하였다. (중략)

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.92-96
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• 2004

Scales, accumulated on semiconductor equipment parts during device fabrication processes, often lower equipment lifetime and production yields. Thus, many equipments parts have be cleaned regularly. In this study, an attempt to establish an effective process for the removal of scales on the sidewall of collimators in the chamber of sputter is made. The EDX analysis revealed that the scales are composed of Ti and TiN with the colummar structure. It was found that the heat-treatment at 700 for 1 min. after the oxide removal in the HF solution, and then etching in the HNO3 : H2SO4 : H2O =4:2:4 solution for 5.5 hrs at 67 was the most effective process for the scale removal.