• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.447-450
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• 2000

In this paper, we report a fabrication of InP-based microstructurs for III-V compound semiconductor micromachining. Vertical liquid phase epitaxy(LPE) system was used in order to grow the Inp/InGaAsP/InP layers. The thicknesses of InP top-layer and InGaAsP were 1$\mu\textrm{m}$ and 0.4$\mu\textrm{m}$ respectively. The fabrication of InGaAsP microstructures involves front side bulk micromachining. The experimental result showed the beams must be carefully aligned in the <110> direction since the lateral etching of the beam in the <110> direction is more faster than that of the beam in the <100> direction.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.242-242
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• 2010

산화 알루미늄($Al_2O_3$) 박막을 p-type Czochralski(CZ) Si 위에 Remote Plasma Atomic Layer Deposition(RPALD)을 이용하여 저온 공정으로 증착하였다. Photolithography 공정으로 grid 패턴을 형성한 후 열 증착기로 알루미늄을 증착하여 MIS-IL (Metal-Insulator-Semiconductor Inversion Layer) solar cell을 제작하였다. 반응소스로는 Trimethylaluminum (TMA)과 $O_2$를 이용하였다. $Al_2O_3$ 박막의 전기적 특성 평가를 위해 MIS capacitor를 제작하여 Capacitance-voltage (C-V), Current-voltage (I-V), Interface state density ($D_{it}$)를 평가하였으며 Solar simulator를 이용하여 MIS-IL Solar cell의 Efficiency을 측정하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.280-283
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• 2004

This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.

• Safety and Health at Work
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• v.15 no.1
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• pp.87-95
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• 2024

Background: This study focuses on assessing occupational risk for the health hazards encountered during maintenance works (MW) in semiconductor fabrication (FAB) facilities. Objectives: The objectives of this study include: 1) identifying the primary health hazards during MW in semiconductor FAB facilities; 2) reviewing the methods used in evaluating the likelihood and severity of health hazards through occupational health risk assessment (OHRA); and 3) suggesting variables for the categorization of likelihood of exposures to health hazards and the severity of health effects associated with MW in FAB facilities. Methods: A literature review was undertaken on OHRA methodology and health hazards resulting from MW in FAB facilities. Based on this review, approaches for categorizing the exposure to health hazards and the severity of health effects related to MW were recommended. Results: Maintenance workers in FAB facilities face exposure to hazards such as debris, machinery entanglement, and airborne particles laden with various chemical components. The level of engineering and administrative control measures is suggested to assess the likelihood of simultaneous chemical and dust exposure. Qualitative key factors for mixed exposure estimation during MW include the presence of safe operational protocols, the use of air-jet machines, the presence and effectiveness of local exhaust ventilation system, chamber post-purge and cooling, and proper respirator use. Using the risk (R) and hazard (H) codes of the Globally Harmonized System alongside carcinogenic, mutagenic, or reprotoxic classifications aid in categorizing health effect severity for OHRA. Conclusion: Further research is needed to apply our proposed variables in OHRA for MW in FAB facilities and subsequently validate the findings.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.6-11
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• 2011

We have developed dissolved ozone decompose system in the used ozonated water for the semiconductor and LCD fabrication processes, which will be base of obtaining core process technology in the high performance, low price semiconductor and LCD fabrications. Using this technology, it is possible for the semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• Journal of the Semiconductor & Display Technology
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• v.6 no.4
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• pp.49-52
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• 2007

As the minimum feature size decrease, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT. Charged monodisperse particles are generated using SMPS (Scanning Mobility Particle Sizer) and deposited on the wafer by electrostatic force. The Experimental results agreed with the simulation results well. We calculate the particles loss in pipe flow theoretically and compare with the experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.6
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• pp.811-821
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• 1998

A new scheduling algorithm for large scale semiconductor processes is addressed. The difficulties of scheduling for semiconductor fabrication processes are mainly due from repeating production of wafers that experience reentrant flows. Sequence branch algorithm (SBA) is proposed for large real scheduling problems when all processing times are deterministic. The SBA is based on the reachability graph of Petri net of which the several defects such as memory consumption and system deadlock are complemented. Though the SBA shows the solution deviating a little from the optimal solution of mixed integer programming, it is adjustable for large size scheduling problems. Especially, it shows a potential that is capable of handling commercial size problems that are intractable with mathematical programming.