• Safety and Health at Work
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• v.15 no.1
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• pp.87-95
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• 2024

Background: This study focuses on assessing occupational risk for the health hazards encountered during maintenance works (MW) in semiconductor fabrication (FAB) facilities. Objectives: The objectives of this study include: 1) identifying the primary health hazards during MW in semiconductor FAB facilities; 2) reviewing the methods used in evaluating the likelihood and severity of health hazards through occupational health risk assessment (OHRA); and 3) suggesting variables for the categorization of likelihood of exposures to health hazards and the severity of health effects associated with MW in FAB facilities. Methods: A literature review was undertaken on OHRA methodology and health hazards resulting from MW in FAB facilities. Based on this review, approaches for categorizing the exposure to health hazards and the severity of health effects related to MW were recommended. Results: Maintenance workers in FAB facilities face exposure to hazards such as debris, machinery entanglement, and airborne particles laden with various chemical components. The level of engineering and administrative control measures is suggested to assess the likelihood of simultaneous chemical and dust exposure. Qualitative key factors for mixed exposure estimation during MW include the presence of safe operational protocols, the use of air-jet machines, the presence and effectiveness of local exhaust ventilation system, chamber post-purge and cooling, and proper respirator use. Using the risk (R) and hazard (H) codes of the Globally Harmonized System alongside carcinogenic, mutagenic, or reprotoxic classifications aid in categorizing health effect severity for OHRA. Conclusion: Further research is needed to apply our proposed variables in OHRA for MW in FAB facilities and subsequently validate the findings.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Design & Manufacturing
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• v.11 no.2
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• pp.25-28
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• 2017

Semiconductor equipment manufacturers desire to enhance efficiency of Sub Fab to increase semiconductor productivity. For this reason, Sub Fab equipment manufacturers are developing Integrated System that combined modules with multiple facilities. Integrated System is required to apply Mount Leveler of Wedge Type in compliance with weight increase compared with existing single equipment and product shape change. This thesis analyzes main design variables of components of Wedge Mount Leveler and carries out structure analysis using ANSYS, finite element analysis program Analysis shows that main design variables of components of Wedge Mount Leveler has self-locking condition by friction force of Wedge and adjusting bolt. Each friction force hinges upon Wedge angle and Friction Coefficient of contact surface and upon the thread angle and Friction Coefficient of contact surface. Also, as a result of carrying out structure analysis of Wedge Mount Leveler, deflection and stress appears in different depending on the height of the level.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.

• Journal of the Korea Society for Simulation
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• v.32 no.3
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• pp.67-74
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• 2023

A semiconductor fabrication facility(FAB) is one of the most capital-intensive and large-scale manufacturing systems which operate under complex and uncertain constraints through hundreds of fabrication steps. To improve fab performance with intuitive scheduling, practitioners have used weighted-sum scheduling. Since the determination of weights in the scheduling significantly affects fab performance, they often rely on simulation-based decision making for obtaining optimal weights. However, a large-scale and high-fidelity simulation generally is time-intensive to evaluate with an exhaustive search. In this study, we investigated three sampling methods (i.e., Optimal latin hypercube sampling(OLHS), Genetic algorithm(GA), and Decision tree based sequential search(DSS)) for the optimization. Our simulation experiments demonstrate that: (1) three methods outperform greedy heuristics in performance metrics; (2) GA and DSS can be promising tools to accelerate the decision-making process.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.3
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• pp.311-318
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• 2000

The importance of the semiconductor industry in Korea has been growing, but the manufacturers are experiencing two major problems: poor optimization of production and low localization ratio of production equipments. Due to the complex manufacturing processes and special features such as OTD (On Time Delivery) and LIPAS (Line Item Performance Against Schedule) possibilities, several attempts to apply MRP or spreadsheet have been failed to meet the expectations. This paper describes the computer modeling technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process, and to build an advanced manufacturing environments. The computer simulation models are built referring the FAB facilities of the National Inter - University Semiconductor Research Center to show the FAB processes and the functions of each process.

• Journal of the Korean Institute of Gas
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• v.22 no.1
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• pp.78-85
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• 2018

In this study, we analyzed risks of the fabrication process equipment and cleanroom for semiconductor/flat panel display (FPD) manufacturing facilities and studied the fundamental safety measures for the risk factors. We examined the explosion proof design models considering the specificity of equipment and environment, and planned to utilize the findings to provide technical standards and grounds for designing and manufacturing related equipment. We believe that this study will contribute to the establishment of technical standards for semiconductor/FPD industry and businesses in many different ways by providing optimized modeling of high-risk explosion site detection, developing safety standards and hazard countermeasures and voluntary activation of safety certification system for operation of fabrication process equipment.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.195-201
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• 2004

In design stage of high precision manufacture/inspect ion FAB building, it is necessary to investigate the vibration allowable limits of high precision equipment and to study a structure dynamic characteristics of C/R and Sub-structure in order to provide a structure vibration environment to satisfy thess allowable limits. The aim of this study is to investigate the dynamic characteristics of PC-Type mock-up structures designed for next TFT LCD FAB through vibration measurement and analysis procedure, therefore, to provide a proper dynamic structure design for high precision manufacture/inspection work process, which satisfy thess allowable limits.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.366-370
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• 2022

A 12 ㎛ pixel-sized 360 × 240 microbolometer focal plane array (MBFPA) was fabricated using a complementary metaloxide-semiconductor (CMOS)-compatible process. To release the MBFPA membrane, an amorphous carbon layer (ACL) processed at a low temperature (<400 ℃) was deposited as a sacrificial layer. The thermal time constant of the MBFPA was improved by using serpentine legs and controlling the thickness of the SiNx layers at 110, 130, and 150 nm on the membrane, with response times of 6.13, 6.28, and 7.48 msec, respectively. Boron-doped amorphous Si (a-Si), which exhibits a high-temperature coefficient of resistance (TCR) and CMOS compatibility, was deposited on top of the membrane as an IR absorption layer to provide heat energy transformation. The structural stability of the thin SiNx membrane and serpentine legs was observed using field-emission scanning electron microscopy (FE-SEM). The fabrication yield was evaluated by measuring the resistance of a representative pixel in the array, which was in the range of 0.8-1.2 Mohm (as designed). The yields for SiNx thicknesses of SiNx at 110, 130, and 150 nm were 75, 86, and 86%, respectively.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.135-140
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• 2003

반도체 제조 공정 중 FAB공정은 수많은 단위공정들로 이루어져 있고, 한 Lot에 대한 모든 공정을 진행하는 데에는 약 1개월 이상이 소요된다. 반도체 산업의 특성상 고객이 원하는 제품을 최단 시간 내에 생산을 해서 적기에 제품을 공급해야만 최대의 수익을 올릴 수가 있다. 그러므로 FAB공정의 공기단축은 반도체 생산에서 중요한 부분이 된다고 할 수 있다. 본 연구는 FAB공정 중 단위공정과 단위공정 사이에서 이루어지는 작업을 라인자동화를 통한 새로운 모델을 적용해서 단위공정에서 소요되는 시간을 단축함으로써, 반도체 제조의 생산성향상 및 공기단축을 목적으로 한다.