• Journal of the Semiconductor & Display Technology
• /
• v.18 no.4
• /
• pp.30-34
• /
• 2019

We analyzed how the features in plasma information based virtual metrology (PI-VM) for SiO₂ etching depth with variation of 5% contribute to the prediction accuracy, which is previously developed by Jang. As a single feature, the explanatory power to the process results is in the order of plasma information about electron energy distribution function (PI_EEDF), equipment, and optical emission spectroscopy (OES) features. In the procedure of stepwise variable selection (SVS), OES features are selected after PI_EEDF. Informative vector for developed PI-VM also shows relatively high correlation between OES features and etching depth. This is because the reaction rate of each chemical species that governs the etching depth can be sensitively monitored when OES features are used with PI_EEDF. Securing PI_EEDF is important for the development of virtual metrology (VM) for prediction of process results. The role of PI_EEDF as an independent feature and the ability to monitor variation of plasma thermal state can make other features in the procedure of SVS more sensitive to the process results. It is expected that fault detection and classification (FDC) can be effectively developed by using the PI-VM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.5
• /
• pp.527-532
• /
• 2024

Physically Unclonable Functions (PUFs) provide a high level of security for private keys using unique physical characteristics of hardware. However, fabricating PUF chips requires numerous semiconductor processes, leading to high costs, which limits their applications. In this work, we introduce a low-cost manufacturing method for PUF security chips. First, surface roughening through wet-etching is utilized to create random variables. Additionally, physical vapor deposition is added to further enhance randomness. After PUF chip fabrication, both Hamming distance (HD) and Hamming weight (HW) are extracted and compared to verify the fabricated chip. It is confirmed that the PUF chip using two different multiple process variables demonstrates superior uniqueness and uniformity compared to the PUF security chip fabricated using only a single process variable.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1997.10a
• /
• pp.935-938
• /
• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.65-65
• /
• 1999

Dry etching technique provides more easy controllability on the etch profile such as anisotropic etching than wet etching process and the results of lots of researches on the characterization of various plasmas or ion beams for semiconductor etching have been reported. Chlorine-based plasmas or chlorine ion beam have been often used to etch several semiconductor materials, in particular Si-based materials. We have studied the effect of He flow rate on the Si and SiO2 dry etching using chlorine-based plasma. Experiments were performed using reactive ion etching system. RF power was 300W. Cl2 gas flow rate was fixed at 58.6 sccm, and the He flow rate was varied from 0 to 120 sccm. Fig. 1 presents the etch depth of si layer versus the etching time at various He flow rate. In case of low He flow rate, the etch rate was measured to be negligible for both Si and SiO2. As the He flow increases over 30% of the total inlet gas flow, the plasma state becomes stable and the etch rate starts to increase. In high Ge flow rate (over 60%), the relation between the etch depth and the time was observed to be nearly linear. Fig. 2 presents the variation of the etch rate depending on the He flow rate. The etch rate increases linearly with He flow rate. The results of this preliminary study show that Cl2/He mixture plasma is good candidate for the controllable si dry etching.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.244-250
• /
• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Journal of Information Display
• /
• v.10 no.3
• /
• pp.111-116
• /
• 2009

In this paper, a plasma-assisted patterning method for the organic layers of organic light-emitting diodes (OLEDs) and its effect on the OLED performances are reported. Oxygen plasma was used to etch the organic layers, using the top electrode consisting of lithium fluoride and aluminum as an etching mask. Although the current flow at low voltages increased for the etched OLEDs, there was no significant degradation of the OLED efficiency and lifetime in comparison with the conventional OLEDs. Therefore, this method can be used to reduce the ohmic voltage drop along the common top electrodes by connecting the top electrode with highly conductive bus lines after the common organic layers on the bus lines are etched by plasma. To further analyze the current increase at low voltages, the plasma patterning effect on the OLED performance was investigated by changing the device sizes, especially in one direction, and by changing the etching depth in the vertical direction of the device. It was found that the current flow increase at low voltages was not proportional to the device sizes, indicating that the current flow increase does not come from the leakage current along the etched sides. In the etching depth experiment, the current flow at low voltages did not increase when the etching process was stopped in the middle of the hole transport layer. This means that the current flow increase at low voltages is closely related to the modification of the hole injection layer, and thus, to the modification of the interface between the hole injection layer and the bottom electrode.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.3
• /
• pp.199-205
• /
• 2006

Patterned sapphire substrates (PSS) were fabricated by a simple wet etching process with $SiO_2$ stripe masks and a mixed solution of $H_2SO_4$ and $H_3PO_4$. GaN layers were epitaxially grown on the PSS under the optimized 2-step growth condition of metalorganic vapor deposition. During the 1st growth step, GaN layers with triangular cross sections were grown on the selected area of the surface of the PSS, and in the 2nd growth step, the GaN layers were laterally grown and coalesced with neighboring GaN layers. The density of threading dislocations on the surface of the coalesced GaN layer was $2{\sim}4\;{\times}\;10^7\;cm^{-2}$ over the entire region. The epitaxial structure of near-UV light emitting diode (LED) was grown over the GaN layers on the PSS. The internal quantum efficiency and the extraction efficiency of the LED structure grown on the PSS were remarkably increased when compared to the conventional LED structure grown on the flat sapphire substrate. The reduction in TD density and the decrease in the number of times of total internal reflections of the light flux are mainly attributed due to high level of scattering on the PSS.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.132-132
• /
• 2015

Virtual metrology (VM) model based on plasma information (PI) parameter for C4F8 plasma-assisted oxide etching processes is developed to predict and monitor the process results such as an etching rate with improved performance. To apply fault detection and classification (FDC) or advanced process control (APC) models on to the real mass production lines efficiently, high performance VM model is certainly required and principal component regression (PCR) is preferred technique for VM modeling despite this method requires many number of data set to obtain statistically guaranteed accuracy. In this study, as an effective method to include the 'good information' representing parameter into the VM model, PI parameters are introduced and applied for the etch rate prediction. By the adoption of PI parameters of b-, q-factors and surface passivation parameters as PCs into the PCR based VM model, information about the reactions in the plasma volume, surface, and sheath regions can be efficiently included into the VM model; thus, the performance of VM is secured even for insufficient data set provided cases. For mass production data of 350 wafers, developed PI based VM (PI-VM) model was satisfied required prediction accuracy of industry in C4F8 plasma-assisted oxide etching process.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2001.04a
• /
• pp.1068-1071
• /
• 2001

Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.320-320
• /
• 2013

Film thickness monitoring with plasma impedance monitoring (PIM) is demonstrated for small area $SiO_2$ RF plasma etching processes in this work. The chamber conditions were monitored by the impedance signal variation from the I-V monitoring system. Moreover, modified principal component analysis (mPCA) was applied to estimate the $SiO_2$ film thickness. For verification, the PIM was compared with optical emission spectroscopy (OES) signals which are widely used in the semiconductor industry. The results indicated that film thickness can be estimated by 1st principal component (PC) and 2nd PC. Film thickness monitoring of small area $SiO_2$ etching was successfully demonstrated with RF plasma harmonic impedance monitoring and mPCA. We believe that this technique can be potentially applied to plasma etching processes as a sensitive process monitoring tool.