• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.438-440
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• 1995

The impedance characteristics and plasma parameters were experimentally studied in a weakly magnetized planar type, inductively coupled plasma (ICP) system. Compared with non-magnetized for system higher power transfer efficiency, stable impedance matching, enhancement of plasma density and higher electron temperature can be obtained. Such improvements are mainly due to the excitation of deeply penetrating electromagnetic wave and reduction of radial loss of electrons. In particulary, $SF_6$ (sulfur hexafluride) plasma shows unstable impedance matching in non-magnetized ICP because electronegativity of $SF_6$ effects on plasma characteristics. But, magnetized inductively coupled $SF_6$ plasma shows enough impedance matching stability to be applicable to the polysilicon etching in semiconductor process.

• Applied Science and Convergence Technology
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• v.23 no.6
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• pp.328-339
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• 2014

In this article, plasma monitoring tools and mulivariate analysis techniques were reviewed. Optical emission spectroscopy was reviewed for a chemical composition analysis tool and RF V-I probe for a physical analysis tool for plasma monitoring. Multivariate analysis techniques are discussed to the sensitivity improvement. Principal component analysis (PCA) is one of the widely adopted multivariate analysis techniques and its application to end-point detection of plasma etching process is discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.410.1-410.1
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• 2014

A soft-lithographic top-down approach is combined with an epitaxial layer transfer process to fabricate high quality III-V compound semiconductor nanowires (NWs) and integrate them on Si/SiO2 substrates, using MBE-grown ultrathin InAs as a source wafer. The channel width of the InAs nanowires is controlled by using solvent-assisted nanoscale embossing (SANE), descumming, and etching processes. By optimizing these processes, the NW width is scaled to less than 50 nm, and the InAs NWFETs has ${\sim}1,600cm^2/Vs$ peak electron mobility, which indicates no mobility degradation due to the size.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.563-570
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• 1990

A silicon pressure sensor made of a full bridge of diffused resistors was designed and fabricated using semiconductor integrated circuit process. Thin diaphragms with 30\ulcorner thickness were obtained using anisotropic wet chemical etching technique. Our device showed strong temperature dependence. Compensation networks are used to compensate for the temperature dependence of the pressure sensor. The bridge supply voltage having positive temperature coefficient by compensation networks was utilized against the negative temperature coefficient of bridge output voltage. The sensitivity fluctuation of pressure sensor before temperature compensation was -1700 ppm/\ulcorner, while it reduced to -710ppm\ulcorner with temperature compensation. Our result shows that the we could develop accurate and reliable pressure sensor over a wide temperature range(-20\ulcorner~50\ulcorner).

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.189-192
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• 2009

The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

• Journal of the Korean institute of surface engineering
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• v.55 no.6
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• pp.328-341
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• 2022

Area selective atomic layer deposition (AS-ALD) is a bottom-up nanopattern fabrication method that can grow the ALD films only on the desired substrate areas without using photolithography and etching processes. Particularly, AS-ALD has attracted great attention in the semiconductor manufacturing process due to its advantage in reducing edge placement error by fabricating self-aligned patterns. In this paper, the basic principles and characteristics of AS-ALD are described. In addition, various approaches for achieving AS-ALD with excellent selectivity were comprehensively reviewed. Finally, the technology development to overcome the selectivity limit of AS-ALD was introduced along with future prospects.

• Laser Solutions
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• v.16 no.4
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• pp.17-23
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• 2013

The research for the development of roll-to-roll printing process is actively underway on behalf of the existing semiconductor process. The roll-to-roll printing system can make the electronic devices to low-cost mass production. This study is performed for developing the manufacturing technology of the printing roll used in the printing process of electronic devices. The indirect laser engraving technology is used to create printable roll and the printable roll is made out of the chrome coated roll after coating copper and polymer on the surface of steel roll, ablating the polymer on the surface of roll and etching the roll. The 3 dimensional laser scanner and roll rotating systems are constructed and the system control program is developed. We have used the fiber laser of 100 W grade, the 3 dimensional laser scanner and the 3 axes moving stage system with a rotating axis. We have found the optimal conditions by performing the laser patterning experiments and can make the minimum line width of $24{\mu}m$ by using the developed 3 dimensional laser scanner system.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1333-1334
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• 2007

Al thin film was the most popular electrode in semiconductor and flat panel display world, because of its electrical conductivity, selectivity and easy to apply to thin film. However, Al thin films were not good to use on the bottom electrode about the crystalline growth of inorganic compound materials such as ZnO, AlN and GaN, because of its surface roughness and melting points. In this paper, we investigated Ar plasma surface treatment of Al thin film to enhance the surface roughness and electrical conductivity using the reactive ion etching system. Several process conditions such as RF power, working pressure and process time were controlled. In results, the surface roughness showed $15.53\;{\AA}$ when RF power was 100 W, working pressure was 50 mTorr and process time was 10 min. Also, we tried to deposit ZnO thin films on the each Al thin films, the upper conditions showed the best crystalline characteristics by x-ray diffraction.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.221-221
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• 2013

Vertical LED (VLED) has been recognized as a way to obtain the high-power LED due to their advantages [1]. However, approximately 4% of the light generated from the active region is extracted, if the light extraction from side walls and back side is neglected because of Fresnel reflection (FR) and total internal reflection (TIR) [2,3]. In this study, the optical simulation of the VLED with the various microstructures was performed. Among them, the microlens having the diameter of 3 ${\mu}m$ and the height of 1.5 ${\mu}m$ shown the best result was chosen, and then, optimized microlens was formed on a GaN template using conventional semiconductor process. Various microstructures were proposed to improve the light extraction efficiency (LEE) of the VLED for the simulation. The LEE was simulated using LightTools based on a Monte Carlo ray tracing. The microstructures with hemisphere, cone, truncated and cylinder pattern having diameter of 3 ${\mu}m$ were employed on the top layer of the VLED respectively. The improvement of the LEE by using the microstructure is 87% for the hemisphere, 77% for the cone, 53% for the truncated, 21% for the cylinder, compared with the LEE of the flat surface at the reflectance of 85%. The LEE was increased by 88% at the height of 1.5 ${\mu}m$, compared with the LEE of the flat surface. We found that the microlens on the top layer is the most suitable for increasing the LEE. In order to apply the proposed microlens on n-GaN surface, we fabricated microlens on a GaN template. A photoresist array having hexagonal-closed packed microlens was fabricated on the GaN template. Then, optimization of etching the GaN template was performed using a dry etching process with ICP-RIE. The dry etching carried out using a gas mixture of Cl2 and Ar, each having a flow rate of 16 sccm and 10 sccm, respectively with RF power of 50 W, ICP power of 900 W and chamber pressure of 2 mTorr was the optimum etching condition as shown in Fig. 2(a).

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.231-237
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• 2014

In this paper, we have proceeded research for failures of semiconductor device stressed by Pressure Cooker Test(PCT). After PCT stress, we found various failures such as delamination between aluminium line and device layers and chemical composition transition of aluminium. We have executed the analysis using the physical and chemical observation equipments. There were the main failures that aluminium loss of aluminium pad is occurred and $Al_xO_y$($Al_2O_3$ or $Al(OH)_3$)) layer is formed abnormally. The primary cause of the failures is reaction of supplied fluorine or chlorine gases and infiltrated moisture during etching process.