• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.61-66
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• 2021

In this study, we studied the alternative of plasma resistant ceramic parts that constitute plasma chambers in the semiconductor dry etching process. MgO-Al₂O₃-SiO₂(MAS) glass was made of 13 types of glass using the Design Of Experiments(DOE) and the effect on thermal properties such as glass transition temperature and crystallization temperature depending on the content of each composition and etching resistance to CF₄/O₂/Ar plasma gas. MAS glass showed excellent plasma resistance and surface roughness up to 20 times higher than quartz glass. As the content of Al₂O₃ and MgO increases, the plasma resistance is improved, and it has been confirmed that it has an inverse relationship with SiO₂.

• 한국레이저가공학회지
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• 제11권1호
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• pp.7-11
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• 2008

Decapsulation technology is useful to inspect EMC of package device and the etching technology enable to check inside of device by removing plastic molding. Chemical etching method is used widely to fabricate a lot of semiconductor. But the method has some disadvantage due to wet process. Proposed method in this paper shows the application possibility such as fast processing time, processing accuracy and dry process. These result was obtained by directly removing of packed EMC using UV laser.

• 한국초전도ㆍ저온공학회논문지
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• 제20권4호
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.142.2-142.2
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• 2015

Plasma etch endpoint detection (EPD) of SiO2 and PR layer is demonstrated by plasma impedance monitoring in this work. Plasma etching process is the core process for making fine pattern devices in semiconductor fabrication, and the etching endpoint detection is one of the essential FDC (Fault Detection and Classification) for yield management and mass production. In general, Optical emission spectrocopy (OES) has been used to detect endpoint because OES can be a simple, non-invasive and real-time plasma monitoring tool. In OES, the trend of a few sensitive wavelengths is traced. However, in case of small-open area etch endpoint detection (ex. contact etch), it is at the boundary of the detection limit because of weak signal intensities of reaction reactants and products. Furthemore, the various materials covering the wafer such as photoresist (PR), dielectric materials, and metals make the analysis of OES signals complicated. In this study, full spectra of optical emission signals were collected and the data were analyzed by a data-mining approach, modified K-means cluster analysis. The K-means cluster analysis is modified suitably to analyze a thousand of wavelength variables from OES. This technique can improve the sensitivity of EPD for small area oxide layer etching processes: about 1.0 % oxide area. This technique is expected to be applied to various plasma monitoring applications including fault detections as well as EPD.

• 한국전자통신학회논문지
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• 제17권6호
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• pp.1175-1180
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• 2022

STI는 반도체 소자의 소형화 및 고집적화에 따른 광역 평탄화를 위한 공정 기술로써 많은 연구가 이루어져 왔다. 본 연구에서는 STI의 profile 개선을 위한 방법으로 STI 건식각 후 HF 용액에 의한 pad oxide 습식각과 O₂+CF₄ 건식각을 제안하였다. 이 공정 기술은 기존의 방법보다 소자의 밀집도에 따른 패턴간의 프로파일 불균형과 누설전류의 개선을 나타내었다. 또한 동일한 STI 깊이와 HLD 증착를 갖는 디바이스에 대하여 CMP 후 HLD 두께를 측정한 결과 디바이스 밀도에 따라 측정값이 다르게 나타났고 이는 CMP 후 디바이스 밀도에 따른 질화막의 두께 차이 및 슬러리의 선택비에 기인됨을 확인하였다.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.130-135
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• 2023

Plasma-resistant ceramic (PRC) is a material used to prevent internal damage in plasma processing equipment for semiconductors and displays. The challenge is to suppress particles falling off from damaged surfaces and increase retention time in order to improve productivity and introduce the latest miniaturization process. Here, we confirmed the effect of suppressing plasma deterioration and reducing the etch rate through surface treatment of existing PRC with an initial illumination level of 200 nm. In particular, quartz glass showed a decrease in etch rate of up to 10%. Furthermore, it is believed that micro-scale secondary particles formed on the microstructure of each material grow as crystals during the fluoridation process. This is a factor that can act as a killer defect when dropped, and is an essential consideration when analyzing plasma resistance. The plasma etching suppression effect of the initial illumination is thought to be due to partial over etching at the dihedral angle of the material due to the sputtering of re-emission of Ar+-based cations. This means that plasma damage due to densification can also be interpreted in existing PRC studies. The research results are significant in that they present surface treatment conditions that can be directly applied to existing PRC for mass production and a new perspective to analyze plasma resistance in addition to simple etching rates.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• Design & Manufacturing
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• 제14권1호
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• pp.36-41
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• 2020

Recently, due to the development of MEMS technology, researches for the production of effective micro structures and shapes have been actively conducted. However, the process technology based on chemical etching has a number of problems such as environmental pollution and time problems due to multi-process. Various processes to cope with this process are being studied, and one of the mechanical etching processes is the powder blasting process. This process is a method of spraying fine particles, which has the advantage of being an effective process in manufacturing hard brittle materials. However, it is also a process that adversely affects the material surface roughness and material properties due to the impact of the injection of fine particles. In this study, after fabricating micro-channels in fused silica glass with excellent optical properties among the hard brittle materials, we used the nano indentation system to analyze the micro parts using nano-particles as well as machinability and surface roughness analysis of the processed surface. The analysis was performed for the effective processing of powder blasting.

• 반도체디스플레이기술학회지
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• 제19권4호
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• pp.28-33
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• 2020

Plasma etching process employs high density plasma to create surface chemistry and physical reactions, by which to remove material. Plasma chamber includes silicon-based materials such as a focus ring and gas distribution plate. Focus ring needs to be replaced after a short period. For this reason, there is a need to find materials resistant to erosion by plasma. The developed chemical vapor deposition processing to produce silicon carbide parts with high purity has also supported its widespread use in the plasma etch process. Silicon carbide maintains mechanical strength at high temperature, it have been use to chamber parts for plasma. Recently, besides the structural aspects of silicon carbide, its electrical conductivity and possibly its enhanced life time under high density plasma with less generation of contamination particles are drawing attention for use in applications such as upper electrode or focus rings, which have been made of silicon for a long time. However, especially for high purity silicon carbide focus ring, which has usually been made by the chemical vapor deposition method, there has been no study about quality improvement. The goal of this study is to reduce surface roughness and depth of damage by diamond tool grit size and tool dressing of diamond tools for precise dimensional assurance of focus rings.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.11-16
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• 2002

본 연구에서는 $SrBi_2Ta_2O_9$ (SBT)박막의 고속식각에 따른 잔류물질 및 식각 손상의 영향을 조사하였다. ICP-RIE (inductively coupled plasma reactive ion etching) 의 ICP power와 CCP(capacitively coupled plasma) power를 변화시키면서 고속식각에 따른 박막의 손상과 열화를 XPS 분석과 Capacitance-Voltage (C-V) 측정을 통하여 알아보았다. ICP와 CCP의 power가 증가함에 따라 식각율이 증가하였고 ICP power가 700 W, CCP power가 200 W 일때 식각율은 900$\AA$/min이었다. 강유전체의 건식식각에 있어서 문제점이 플라즈마에 의한 강유전체 박막의 열화인데 반응가스 $Ar/C1_2/CHF_3$를 20/14/2의 비율로 사용하고 ICP와 CCP power를 각각 700w와 200w로 사용하였을 때 전혀 열화되지 않는 강유전체 박막의 특성을 얻을 수 있었다. 본 연구 결과는 Metal-Ferroelectric-Semiconductor (MFS) 또는 Metal-Ferroelectric-Insulator-Semiconductor (MFIS) 구조를 가지는 단일 트랜지스터형 강유전체 메모리 소자를 만드는데 건식 식각이 응용될 수 있음을 보여준다