• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.122-130
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• 2015

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in $0.13{\mu}m$ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum $98.1dB{\Omega}$ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is $1.9mm{\times}2.2mm$ for 4-channel. The power dissipation is 47.64 mW/1ch.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.100-104
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• 2019

We have investigated the feasibility of fabricating fine stripes using needle coating for potential applications in solution-processed organic light-emitting diodes (OLEDs). To this end, we have employed an aqueous poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) solution that has been widely used as a hole injection layer (HIL) of OLEDs and performed needle coatings by varying the process parameters such as the coating gap and coating speed. As expected, the stripe width is reduced with increasing coating speed. However, the central thickness of the stripe is rather increased as the coating speed increases, which is different from other coating processes such as slot-die and blade coatings. It is due to the fact that the meniscus formed between the needle tip and the substrate varies depending sensitively on the coating speed. It is also found that the stripe width and thickness are reduced with increasing coating gap. To demonstrate its applicability to OLEDs, we have fabricated a red OLED stripe and obtained light emission with the width of about 90㎛.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.1-5
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• 2021

Sleep apnea refers to a condition in which a person does not breathe during sleep, and is a dangerous symptom that blocks oxygen supply in the body, causing various complications, and the elderly and infants can die if severe. In this paper, we present an algorithm that classifies sleep breathing by analyzing the intensity of breathing with images alone in preparation for the risk of sleep apnea. Only the chest of the person being measured is set to the Region of Interest (ROI) to determine the breathing strength by the differential image within the corresponding ROI area. The adult was selected as the target of the measurement and the breathing strength was measured accurately, and the difference in breathing intensity was also distinguished using depth information. Two videos of sleeping babies also show that even microscopic breathing motions smaller than adults can be detected, which is also expected to help prevent infant death syndrome (SIDS).

• Design & Manufacturing
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• v.14 no.4
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• pp.58-64
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• 2020

Lately, the development of the semiconductor industry has led to the miniaturization of electronic devices. Therefore, semiconductor wafers of very thin thickness that can be used in Multi-Chip Packages are required. There is active research on the backgrinding process to reduce the thickness of the wafer. The backgrinding process polishes the backside of the wafer, reducing the thickness of the wafer to tens of ㎛. The equipment that performs the backgrinding process requires ultra-precision. Currently, there is no full auto backgrinding equipment in Korea. Therefore, in this study, ultra-precision backgrinding equipment was designed. In addition, finite element analysis was conducted to verify the equipment design validity. The deflection and structural stability of the backgrinding equipment were analyzed using finite element analysis.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.155-160
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• 2023

The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.1-7
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• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.32 no.3
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• pp.99-109
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• 2009

Negative binomial yield model for semiconductor manufacturing consists of two parameters which are the average number of defects per die and the clustering parameter. Estimating the clustering parameter is quite complex because the parameter has not clear closed form. In this paper, a Bayesian approach using Markov Chain Monte Carlo is proposed to estimate the clustering parameter. To find an appropriate estimation method for the clustering parameter, two typical estimators, the method of moments estimator and the maximum likelihood estimator, and the proposed Bayesian estimator are compared with respect to the mean absolute deviation between the real yield and the estimated yield. Experimental results show that both the proposed Bayesian estimator and the maximum likelihood estimator have excellent performance and the choice of method depends on the purpose of use.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.865-869
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• 1997

In recent years, there has been increasing demand of ultra-fine grain graded cemented tungsten carbide material with high hardness and toughness which is used as high speed cutting tool for development in semiconductor, electronics and die/mold industry, which bring into limelight high-precision, high-efficient machining of sculptured surfaces. This paper deals with the performance of variation in the ultra-fine grain graded cemented tungsten carbide material such as grain size, hardness and density varied according to the volume of added elements, Co or TaC, and he changing of mixing, sintering process. Also, the performance of developing material with uniformed grain size of 0.5${\mu}{\textrm}{m}$ is compared with other domestics' & foreign companies' with analyzing and cutting performance testing.