• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.99.4-99
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• 1998

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.4
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• pp.35-46
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• 2000

Semiconductor technology includes from semiconductor materials, design, fabrication, handling of process equipments, reliability test to packaged semiconductor devices. Our departmental curriculum is organized with 2-years/6-quarters system of Ulsan College: the understanding for the fundamental of semiconductor is carried out in the first academic year and the training for the design skill on semiconductor devices will be focused in the second academic year. The main focus is reflected on the worldwide trend on the design engineering of semiconductor devices and considered for the market establishment on design engineers trained by the lab-oriented practice as well as the fundamental of semiconductor technology.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.87-89
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• 2006

This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.98.1-98
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• 1998

• Journal of the Korea Society of Computer and Information
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• v.22 no.10
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• pp.1-7
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• 2017

In this paper, the separation force measuring system is developed. The separation force aries due to adhesive strength between semiconductor epoxy molding compound(EMC) and the metal plate in semiconductor formed plate. In general, when removing the metal plate in semiconductor formed plate from semiconductor epoxy molding compound, excessive strength can result in a increase in semiconductor defect rates, or conversely, if too little force is exerted on the metal plate in semiconductor formed plate, the semiconductor production rates can decrease. In this study, the design criteria for the selection of the AC servo motor, the role of the ball screw, the relationship between the load cell and the ball screw, and the rate of deceleration are given. In addition, minimizing the reject rate of semiconductors and maximizing the semiconductor production rate are achieved through the standardization of the collected separation force data measured by the proposed system.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.