• 대한전자공학회논문지TE
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• 제37권5호
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• pp.7-16
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• 2000

본 논문은 고속 지수 선택기를 이용한 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 구현에 관하여 기술하였다. 본 제산/스퀘어-루트는 처리 속도 25㎒를 갖는 여분 이진수의 가산 방식을 사용하여 올림수 지연을 제거함으로써 비트 크기에 관계없이 일정한 시간으로 가산을 수행한다. 각각의 반복 단계에 널리 사용된 제산과 스퀘어-루트에 대해 16-비트 VLSI 회로를 설계하였다. 이것은 매번 16개 클럭마다 시프트된 이진수를 여분 가산하여 제산 및 스퀘어-루트를 실행한다. 또한 이 회로는 비복원 방법을 사용하여 지수 비트를 얻는다. 지수 선택 논리의 간단한 회로를 구현하기 위하여 나머지 비트의 주요 세 자리를 사용하였다. 결과적으로, 이 회로의 성능은 새로운 지수 선택 가산 논리를 적용하여 지수 결정 영역을 병렬 처리함으로써 한층 더 연산 처리 속도를 높인 것이다. 이전에 동일한 알고리즘을 사용하여 제안된 설계보다 13% 빠른 속도 증가를 보였다.

• Journal of Power Electronics
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• 제7권4호
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• pp.343-352
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• 2007

This paper proposes a modularized charge equalization converter for hybrid electric vehicle (HEV) lithium-ion battery cells, in which the intra-module and the inter-module equalizer are Implemented. Considering the high voltage HEV battery pack, over approximately 300V, the proposed equalization circuit modularizes the entire $M^*N$ cells; in other words, M modules in the string and N cells in each module. With this modularization, low voltage stress on all the electronic devices, below roughly 64V, can be obtained. In the intra-module equalization, a current-fed DC/DC converter with cell selection switches is employed. By conducting these selection switches, concentrated charging of the specific under charged cells can be performed. On the other hand, the inter-module equalizer makes use of a voltage-fed DC/DC converter for bi-directional equalization. In the proposed circuit, these two converters can share the MOSFET switch so that low cost and small size can be achieved. In addition, the absence of any additional reset circuitry in the inter-module equalizer allows for further size reduction, concurrently conducting the multiple cell selection switches allows for shorter equalization time, and employing the optimal power rating design rule allows fur high power density to be obtained. Experimental results of an implemented prototype show that the proposed equalization scheme has the promised cell balancing performance for the 7Ah HEV lithium-ion battery string while maintaining low voltage stress, low cost, small size, and short equalization time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권4호
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• pp.1390-1405
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• 2014

This paper investigates optimal relay selection and power allocation under an aggregate power constraint for cooperative wireless sensor networks assisted by amplify-and-forward relay nodes. By considering both transmission power and circuit power consumptions, the received signal-to-noise ratio (SNR) at the destination node is calculated, based on which, a relay selection and power allocation scheme is developed. The core idea is to adaptively adjust the selected relays and their transmission power to maximize the received SNR according to the channel state information. The proposed scheme is derived by recasting the optimization problem into a three-layered problem-determining the number of relays to be activated, selecting the active relays, and performing power allocation among the selected relays. Monte Carlo simulation results demonstrate that the proposed scheme provides a higher received SNR and a lower bit error rate as compared to the average power allocation scheme.

• ETRI Journal
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• 제34권3호
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1751-1753
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• 2002

Arc phenomena occur in the air, must be more diverse than vacuum and SF6. An air arc interruption method has been used in low rated voltage circuit breakers such as ACB, MCCB and MCB. Most of them have the arc chamber composed of arc chutes and lateral walls that made of many kinds of materials. Therefore, the criterion of material selection is necessary for breaking capacity improvement. So, we selected some contact and lateral wall materials, and carried out short circuit tests. Especially, some parameters of arc plasma properties were very different each polymeric wall material.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.952-953
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• 2006

As car industry takes the DMB, geographical feature information and Internet service recently, the need of an electricity energy is the trend to increase. But existing 12V car electricity system is difficult to be satisfied rapidly increasing electricity need. A relation component company is adding the spur at a high electricity system development. In this paper we accomplished the hi-directional DC-DC Converter for high electricity system composed 42V configuration device. Through a simulation experiment, We looked into the control method and the operation characteristic of the circuit, We accomplished the comparison analysis for fit topoloy selection.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.205-208
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• 2003

Maximum short circuit current of modern power system is becoming so large that the current should transmission capability. Although there are various kinds of method to solve this, approached from super conductivity Fault Current Limiter application viewpoint among them. High Temperature Superconductor-Fault Current Limiter (HTS-FCL) development is progressing according to HTS technology development, and system application is tried. For actual system application of such super conductivity FCL, an efficient method to find FCL locations suitable for reduction of short circuit currents of more than one fault location is developed.

• 대한전기학회논문지
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• 제41권6호
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• pp.588-599
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• 1992

This paper describes the variable speed drive of an induction motor by the line commutated inverter, which is operated in the forced commutation mode from start-up to operating point of load commutation. A novel forced-commutation circuit is proposed in this paper. The selection range of leading condenser to decide load commutation starting point is simulated by the sampling data of a general purpose IM and a high speed IM. The experiment to drive IM by a line commutated inverter with the proposed forced commutated circuits is performed. There was no problem in driving IM from standstill to starting point of load commutation by a line commutated inverter with forced commutation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
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• pp.321-323
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• 2003

Maximum short circuit current of modern power system is becoming so large that the current should transmission capability. Although there are various kinds of method to solve this, approached from super conductivity Fault Current Limiter application viewpoint among them. High Temperature Superconductor-Fault Current Limiter(HTS-FCL) development is progressing according to HTS technology development, and system application is tried. For actual system application of such super conductivity FCL, an efficient method to find FCL locations suitable for reduction of short circuit currents of more than one fault location is developed.