• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.376-378
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• 1994

The turn-off behavior of the GTO Thyristor by its nature differs very much from that of other power f semiconductor switching devices. So canful attention should be paid in designing the GTO snubber circuit. This paper presents the effect of turn-off snubber circuit elements on the switching characteristics of the GTO, and describes considerations and criteria for the selection of the snubber component values.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1293-1296
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• 2008

As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.7-12
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• 1989

This paper describes the design and development of a PWM electronic controller for a high performance Pneumatic Actuation System. The task includes the design of a closed center valve circuit for minimum gas consumption, the selection of optimum values for key parameters in the PWM circuit, and the design of lag-lead compensation circuit. These were carried out through specific experiments using a prototype pneumatic actuation system. The final performance obtained with the actuation system confirmed the successful design of the developed PWM electronic controller.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.23-30
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• 2011

This paper presents a Single-Inductor Multiple-Output (SIMO) DC-DC Converter with a negative feedback selection circuit to improve a regulation property at light load and to generate independent multiple outputs. The conventional SIMO DC-DC converter with a fixed negative feedback circuit cannot regulate correctly at light load. The SIMO DC-DC converter with the proposed negative feedback selection circuit has been designed in 0.35um 2-poly 3-metal BCDMOS. This converter is dual output boost converter with the 1.5V input and 2.5V, 3.0V output. The power conversion efficiency varies from 59% at 10mA loads to 85% at 50mA loads.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1298-1305
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• 2016

This paper presents the development of a short-circuit protection mechanism on a high voltage switch (HVS) board which is built by a series connection of semiconductor switches. The HVS board is able to quickly detect and limit the peak fault current before the signal board triggers off a gate signal. Voltage clamping techniques are used to safely turn off the short-circuit current and to prevent overvoltage of the series-connected switches. The selection method of the main devices and the development of the HVS board are described in detail. Experimental results have demonstrated that the HVS board is capable of withstanding a short-circuit current at a rated voltage of 10kV without a di/dt slowing down inductor. The corresponding short-circuit current is restricted to 125 A within 100 ns and can safely turn off within 120 ns.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.367-376
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• 2012

This paper describes a Adaptive Impedance Tuning Circuit which can be adaptively tuned between circuit's characteristic impedance and the arbitrary load impedance. The Adaptive Impedance Tuning Circuit is consisted of such parts as mismatch sensor, impedance tuner and tuning algorithm. Each parts's design methods proposed in other papers are compared with their advantages and disadvantages. And we propose simple design method for Adaptive Impedance Tuning Circuit using a ${\lambda}/4$ transmission line and ${\pi}$-network. Calculation formulas and selection algorithm from calculated values of a complex load impedance are proposed and simulation using induced calculation formulas and selection algorithm is performed. Simulation results show good agreement with theoretical predictions.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.1
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• pp.10-15
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• 1990

This paper presents an algorithm that can compute equivalent impedance effctively in computing 3-phase short circuit current which would be generated in power systems. Also this paper proposes a method that can decide the capacity of circuit breaker by analysing the fault current distribution probabilistically when the fault point of specificed line varies. The efficiency of the algorithm was verified by applying the proposed method to IEEE-6bus system and IEEE-30bus system, and probabilistic fault analysing method is verified economic in facility investment by deciding the proper capacity of circuit breaker.