• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.123-125
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• 2004

The importance for Internet security has being increased and the Internet Protocol Security (IPSec) standard, which incorporates cryptographic algorithms, has been developed as one solution to this problem. IPSec provides security services in IP-Layer using IP Authentication Header (AH) and IP Encapsulation Security Payload (ESP). In this paper, we propose IPSec cryptographic processor design based AMBA architecture. Our design which is comprised Rijndael cryptographic algorithm and HAMC-SHA-1 authentication algorithm supports the cryptographic requirements of IP AH, IP ESP, and any combination of these two protocols. Also, our IPSec cryptographic processor operates as AMBA AHB Slave. We designed IPSec cryptographic processor using Xilinx ISE 5.2i and VHDL, and implemented our design using Xilinx's FPGA Vertex XCV600E.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.5
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• pp.67-77
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• 2006

Radio Frequency IDentification (RFID) will soon become an important technology in various industries. Therefore, security mechanisms for Rm systems are emerging crucial problems in RFID systems. In order to guarantee privacy and security, it is desirable to encrypt the transferred data with a strong crypto algorithm. In this paper, we present the ultra-light weight Advanced Encryption Standard (AES) processor which is suitable for RFID tags. The AES processor requires only 3,992 logic gates and is capable of both 128-bit encryption and decryption. The processor takes 446 clock cycles for encryption of a 128-bit data and 607 clock cycles for decryption. Therefore, it shows 55% improved result in encryption and 40% in decryption from previous cases.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Korea Society of Computer and Information
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• v.25 no.6
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• pp.73-79
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• 2020

Nowadays, with the rapid spread of streaming services in the internet world, security vulnerabilities are also increasing rapidly. For streaming security, this paper proposes a PN(pseudo-random noise) distributed structure-based security processor for web streaming contents(SP-WSC). The proposed SP-WSC is basically a PN distributed code algorithm designed for web streaming characteristics, so it can secure various multimedia contents. The proposed SP-WSC is independent of the security vulnerability of the web server. Therefore, SP-WSC can work regardless of the vulnerability of the web server. That is, the SP-WSC protects the multimedia contents by increasing the defense against external unauthorized signals. Incidentally it also suggests way to reduce buffering due to traffic overload.

• Journal of Industrial Technology
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• v.21 no.B
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• pp.107-116
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• 2001

The speech includes various kinds of information : language information, speaker's information, affectivity, hygienic condition, utterance environment etc. when a person communicates with others. All technologies to utilize in real life processing this speech are called the speech technology. The speech technology contains speaker's information that among them and it includes a speech which is known as a speaker recognition. DTW(Dynamic Time Warping) is the speaker recognition technology that seeks the pattern of standard speech signal and the similarity degree in an inputted speech signal using dynamic programming. ln this study, using TMS320C32 DSP processor, we are to embody this DTW and to construct a security system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.85-98
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• 2003

Computational power of IC chip is improved day after day producing IC chips holding co-processor continuously. Also a lot of wireless terminals which IC chip embedded in are produced in order to provide simple and various services in the wireless terminal market. However it is difficult to apply the key distribution protocol under wired communication environment to wireless communication environment. Because the computational power of co-processor embedded in IC chip under wireless communication environment is less than that under wired communication environment. In this paper, we propose the hey distribution protocol appropriate for wireless communication environment which diminishes the computational burden of server and client by using co-processor that performs cryptographic operations and makes up for the restrictive computational power of terminal. And our proposal is satisfied with the security requirements that are not provided in existing key distribution protocol.