• 한국세라믹학회지
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• 제36권4호
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• pp.417-424
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• 1999

Laser lapping of diamond films is performed with focused beam of copper vapor laser. Both spherical and rod-shape laser beam are used. Diamond surface is scanned at various scan speeds(0,125, 0.5, 0.75 mm/sec) and baem shifts (5, 10, 20, 40, 100$\mu\textrm{m}$) At 0.125 mm/sec 10$\mu\textrm{m}$ scan condition the level difference of di-amond surface of about 700$\mu\textrm{m}$ over 20 mm is reduced to 200$\mu\textrm{m}$ In addition surface roughness is also im-proved from 3.53$\mu\textrm{m}$ to 2.47$\mu\textrm{m}$ at 5$\mu\textrm{m}$ beam shift. But at higher beam shift than 10$\mu\textrm{m}$ laser scan makes the surface rougher which is considered to be due to the non uniform spatial distribution of laser en-ergy. It is concluded that homogenized laser beam with high average power is needed for large area laser lapping of diamond films at appreciable rates.

• The Journal of Advanced Prosthodontics
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• 제11권5호
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• pp.271-279
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• 2019

PURPOSE. The newest technologies for digital implant impression (DII) taking are developing rapidly and showing acceptable clinical results. However, scientific literature is lacking data from clinical studies about the accuracy of DII. The aim of this study was to compare digital and conventional dental implant impressions (CII) in a clinical environment. MATERIALS AND METHODS. Twenty-four fixed zirconia restorations supported by 2 implants were fabricated using conventional open-tray impression technique with splinted transfers (CII group) and scan with Trios 3 IOS (3Shape) (DII group). After multiple verification procedures, master models were scanned using laboratory scanner D800 (3Shape). 3D models from conventional and digital workflow were imported to reverse engineering software and superimposed with high resolution 3D CAD models of scan bodies. Distance between center points, angulation, rotation, vertical shift, and surface mismatch of the scan bodies were measured and compared between conventional and digital impressions. RESULTS. Statistically significant differences were found for: a) inter-implant distance, b) rotation, c) vertical shift, and d) surface mismatch differences, comparing DII and CII groups for mesial and distal implant scan bodies ($P{\leq}.05$). CONCLUSION. Recorded linear differences between digital and conventional impressions were of limited clinical significance with two implant-supported restorations.

• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권2호
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• pp.93-101
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• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• 한국정보처리학회논문지
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• 제1권2호
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• pp.272-278
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• 1994

본 논문에서는 BIST(Built-In Self Test)시 순서회로내의 조합회로를 pseudoexhaustive 시험하는데 필요한 테스트 패턴 생성기와 응답 분석기를 제안한다. 제안하는 테스트 패턴 생성기는 테스트 패턴의 초기값을 스캔 인 할 수 있고, exhaustive test pattern 을 생성할 수 있다. 또한, 응답 분석기는 회로의 응답을 분 석할 수 있을 뿐만 아니라 응답 결과를 스캔 아웃할 수 있다. 이러한 테스트 패턴 생 성기와 응답분석기는 SRL과 LFSR을 결합하여 설계하였다.

• 대한화학회지
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• 제25권2호
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• pp.103-109
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• 1981

큰 입력지향을 갖는 20개의 sample and hold가 MOSFET으로 switching되는 간편하면서도 비용이 적게드는 analog 기억장치를 제작하였다. 이것은 digital로 3KHz.까지 임의로 조절되는 shift register로 연결되어 있다. 이 장치의 유용성을 보이기 위해 square와 sine파 및 fast-scan voltammetry와 differential pulse polarography의 전류-시간 변화와 같은 전기화학적 실험을 행하였다.

• KIEE International Transactions on Electrophysics and Applications
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• 제5C권4호
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• pp.161-164
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• 2005

Viologen has been extensively investigated in the paper because their well-behaved electrochemistry has led to their use in a variety of theses, including the electron acceptor for the electric charge delivery mediation of the devices. It was formed monolayer in QCM by self-assembly method. We could know the adsorbed mass of viologen molecules from the frequency shift. We calculated that the adsorbed mass was about 196 [$ng/cm^2$]. We studied the electron transfer property of viologen by the cyclic voltammetry among the electrochemical process so we changed an anion like 0.1 M $NaClO_4$ and $Na_3PO_4$ electrolyte solution and investigated the interrelationship between scan rate and peak current when scan rates were increased twice.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1996년도 추계학술대회
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• pp.157-160
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• 1996

In this paper, reconstruction algorithms of spiral scan imaging which has been used for ultra fast magnetic resonance imaging have been reviewed, and some simulation results using two different algorithms are reported. Since the trajectory of the spiral scan in k-space is the spiral, reconstruction of the spiral scan is not as straight forward as that used in Fourier imaging technique where the sampling points are usually on the rectangular grids. Originally the reconstruction of the spiral scan imaging was based on the convolution backprojection algorithm modified with a shift term, however, some other reconstruction techniques have also been tried by remapping sampling points from spiral trajectory to Cartesian grids. Some experimental aspects of MR spiral scan imaging will also be addressed.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.43-48
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• 2008

일반적으로 자체 테스트 동작은 입력 벡터들 사이에 상호 연관성이 없기 때문에 더 많은 전력을 소비하는 것으로 알려져 있다. 이러한 점은 회로에 손상을 유발할 뿐 아니라 배터리 수명에도 악영향을 미치기 때문에 반드시 해결되어야 할 과제 중 하나이다. 이를 위해 본 논문에서는 새로운 방식의 BIST(Built-In Self Test) 구조를 제안하여 테스트 동작에서의 천이를 감소시키고, 이를 통해 전력소모를 줄이고자 한다. 제안하는 구조에서는 LFSR(Linear Feedback Shift Register)을 통해 생성되는 pseudo-random 테스트 벡터가 스캔 경로로 들어가기 전에 3 bit씩 모아 더 적은 천이를 가지는 4 bit의 패턴으로 변형한다. 이러한 변형과 그에 대한 복원 과정은 기존의 스캔 BIST 구조에서 Bit Generator와 Bit Dropper라는 모듈을 추가하여 간단히 구현하였다. 제안하는 구조를 ISCAS'89 benchmark 회로에 적용한 결과 약 62%의 천이 감소를 확인하였고 이를 통해 제안하는 구조의 효율성을 검증하였다.

• 전자공학회논문지C
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• 제36C권2호
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• pp.14-25
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• 1999

인쇄 회로 보드 수준의 테스팅을 위해 제안된 IEEE 표준 1149.1은 보드상의 테스트 지점에 대한 제어용이도와 관측용이도를 향상시켜 보드의 테스트를 용이하게 해준다. 그러나, 경계 주사 환경에서는 테스트 입력과 테스트 결과에 따른 데이터가 하나의 주사 연결에 의해서 직렬로 이동된다. 이는 테스트 적용시간을 증가시키고 따라서 테스트에 드는 비용을 증가시킨다. 테스트에 소모되는 시간을 줄이기 위해 병렬로 다중주사 경로를 구성하는 방법이 제안되었다. 하지만 이는 여분의 입출력 핀과 내선을 필요로 한다. 더구나 IEEE 표준 1149.1은 주사 경로 상에 있는 IC들의 병렬 동작을 지원하지 않기 때문에 표준에 맞게 설계하기가 어렵다. 본 논문에서는 하나의 테스트 버스로 두 개의 주사 경로를 동시에 제안하는 다중 주사 경로 접근 알고리즘에 기초하여 적은 면적 오버헤드를 가지고 빠른 시간 내에 보드를 테스트할 수 있는 새로운 보드수준의 내장된 자체 테스트 구조를 구현하였다. 제안된 내장된 자체 테스트 구조는 두 개의 주사 경로에 대한 테스트 입력과 테스트 결과를 이동시킬 수 있으므로 테스트에 소모되는 시간을 줄일 수 있고 또한 테스트 입력의 생성과 테스트 결과의 분석에 소모되는 비용을 줄일 수 있다.