• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.309-324
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• 1987

In recent years has been an increasing interest with respect to using the discrete cosine transform(DCT) of which performance is found close to that of the Karhumen-Loeve transform, known to be optimal in the area of digital image processing for tha purpose of the image data compression. Among most of reported algorithms aimed at lowering the coputation complexity. Chen's algorithm is is found to be most popular, Recently, Lee proposed a now algorithm of which the computational complexity is lower than that of Chen's. but its performance is significantly degraded by FWL(Finite-Word-Lenght) effects as a result of employinga a fixed-poing arithmetic. In this paper performance evaluation of these two algorithms and error analysis of FWL effect are described. Also a scaling technique which we call Up & Down-scaling is proposed to allevaiate a performance degradation due to fixed-point arithmetic. When the 16x16point 2DCT is applied on image data and a 16-bit fixed-point arithmetic is employed, both the analysis and simulation show that is colse to that of Chen's.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.

• Journal of Korea Multimedia Society
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• v.10 no.7
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• pp.893-901
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• 2007

Since real-time multimedia applications requiring duality-of-service guarantees are spreading over mobile and wireless networks, energy efficiency in wireless channels is becoming more important. Energy consumption in the channels can be reduced with decreasing the rate of scheduler's outgoing link by means of Dynamic Modulation Scaling (DMS). This paper proposes a fair queuing algorithm, termed Rate Efficient Fair Queuing (REFQ), in order to reduce the outgoing link's rate, which is based on the Latency-Optimized Fair Queuing algorithm developed to enhance Weighted Fair Queuing (WFQ). The performance evaluation result shows that REFQ does decrease the link rate by up to 35% in comparison with that in WFQ, which results in reducing the energy consumption by up to 90% when applied to the DMS based radio modem.

• International Journal of Railway
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• v.4 no.4
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• pp.109-115
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• 2011

An analysis and design method for reducing aerodynamic noise in high-speed trains based on biomimetics of noiseless flight of owl is proposed. Five factors related to the morphology of the flight feather have been selected, and the candidate optimal shape of the flight feather is determined. The turbulent flow field analysis demonstrates that the optimal shape leads to diminished vortex formation by causing separation of the flow as well as allowing the fluid to climb up along the surface of the flight feather. To determine the effect of scaling of the owl's flight feather on the noise reduction, a two-fold and a four-fold scaled up model of the feather are constructed, and the numerical simulations are carried out to obtain the aerodynamic noise levels for each scale. Original model is found to reduce the noise level by 10 dBA, while two-fold increase in length dimensions reduces the noise by 12 dBA. Validation of numerical solution using wind tunnel experimental measurements is presented as well.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.203-205
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• 2004

A soft error rate neutrons is a growing problem for terrestrial integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1379-1382
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• 2003

Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5％ energy savings than DPM-S.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.107-108
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• 2007

In this paper, a cosine-modulated filter bank with a modified synthesis part is proposed for arbitrary scaling of images, whereby down/up-sampling kernels based on a compactly supported sampling function (CSSF) are utilized. Also, an optimized adaptive interpolation technique is incorporated into the filter bank structure to compensate for quality degradation arising in scaled images. Finally, simulation results verify that high quality images with arbitrary sizes can be obtained by applying the proposed approach.

• Proceedings of the Korean Society of Computer Information Conference
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• 2015.07a
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• pp.45-48
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• 2015

오늘날 하드웨어의 발전으로 인해 영상 해상도는 FHD를 넘어 4K UHD 이상의 영상 해상도가 사용화되고 있다. 하지만 Edge Map을 만들기 위해 일반적으로 사용하는 함수들은 Convolution 함수 일종으로서 영상의 해상도가 높을수록 더 많은 Complexity를 요구한다. 또한 현재 주요 영상 압축 기술인 JPEG, H.264/AVC High efficiency video coding(HEVC)같은 기법들은 자연 영상을 중점으로 개발되어 있어 Edge map 압축에 있어 자연 영상만큼의 효율을 보여주지 못하고 있다. 본 논문은 원 영상을 Down Scaling한 뒤 이미지를 다시 원래 사이즈로 Up Scaling하여 두 영상의 차를 이용한 Edge Map을 생성하는 새로운 방법을 소개한다. 생성된 Edge Map의 특성인 Histogram 값의 분포가 0을 중심으로 Gaussian 분포를 가지는 것을 이용한 Zero Based 코덱을 제안한다. 제안된 알고리즘을 이용하여 고 해상도 영상에서도 빠르게 Edge Map을 생성하고 제안한 코덱을 통해 해당 Edge map을 압축한 결과 다른 압축 기술보다 더 뛰어난 성능을 보여주었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.448-449
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• 2022

In the image upscaling field, the method using deep learning is showing better results than using the interpolation method. And for hologram upscaling, using deep learning is showing better results than general interpolation. In this paper, the network structure and learning results are analyzed. The learning results are compared by adjusting the depth of the network and the number of channels at the same weight.