• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.1-16
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• 1995

The performance of a computer system depends on the system architecture and workload, and the high performance required in many applications can be achieved by the scalability of the system architecture and workload. This paper presents scalable workload, a performance metric of scalable speedup and hierarchical modeling for the scalable computer system as well as the development of the object-oriented simulator spmplC++ Which is an advanced C++ version of the discrete event-driven simulation environment smplE. In addition, this paper presents two examples of applying scalable speedup, hierarchical modeling and simulator smplC++ to analyze the performance effect of the sclcbility in a multiprocessor system and a network-based client/server system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Journal of Broadcast Engineering
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• v.17 no.6
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• pp.976-989
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• 2012

In this paper, we propose an efficient motion prediction architecture and DPB design mechanism for scalable multi-view video coding which is implemented by integrating SVC and MVC coding algorithms. In the proposed motion prediction architecture, we employ pictures associated with other views as a candidate for reference picture for improved motion prediction performance. By the proposed prediction architecture, we could enormously reduce the size of compressed video data. When performing scalable multi-view video coding, an integrated DPB design mechanism is also proposed. It is shown by various simulations that the proposed motion prediction architecture for scalable multi-view video coding can result in reduced data size in the compressed bitstream.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.621-627
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• 2010

This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.353-356
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• 2002

In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• ETRI Journal
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• v.30 no.2
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• pp.205-215
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• 2008

Many control schemes have been proposed for flow-level traffic control. However, flow-level traffic control is implemented only in limited areas such as traffic monitoring and traffic control at edge nodes. No clear solution for end-to-end architecture has been proposed. Scalability and the lack of a business model are major problems for deploying end-to-end flow-level control architecture. This paper introduces an end-to-end transport architecture and a scalable control mechanism to support the various flow-level QoS requests from applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.3
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• pp.77-83
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• 2000

This paper presents a new modular multiplier for Montgomery multiplication using iterative small carry save adder. The proposed multiplier is more flexible and suitable for long bit multiplication due to its scalable property according to design area and required computing time. We describe the word-based Montgomery algorithm and design architecture of the multiplier. Our analysis and simulation show that the proposed multiplier provides area/time tradeoffs in limited design area such as IC cards.

• ETRI Journal
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• v.18 no.3
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• pp.107-125
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• 1996

In this paper, we define the general requirements of ATM switching systems such as scalability, distributed fashion, and modularity. Also we propose a practical implementation of a scalable ATM switching system whose capacity can be easily expanded. Firstly, the architecture of the system is discussed with an emphasis on system scalability, modularity of subsystems and the simple control network of the design requirements. Secondly, we suggest the three types of distributed call/connection control schemes that are suitable for our switching system. We also estimate their call processing capacity on the average and make a comparison of them under the various system architectures. Since our scalable switching system can be constructed to perform the call processing functions on the various levels of the system capacity, it has much adaptability at the various evolution phases or regions of the network environment.

• ETRI Journal
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• v.35 no.6
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• pp.990-1000
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• 2013

This paper describes the scalable extension of High Efficiency Video Coding (HEVC) to provide flexible high-quality digital video content services. The proposed scalable codec is designed on multi-loop decoding architecture to support inter-layer sample prediction and inter-layer motion parameter prediction. Inter-layer sample prediction is enabled by inserting the reconstructed picture of the reference layer (RL) into the decoded picture buffer of the enhancement layer (EL). To reduce the motion parameter redundancies between layers, the motion parameter of the RL is used as one of the candidates in merge mode and motion vector prediction in the EL. The proposed scalable extension can support scalabilities with minimum changes to the HEVC and provide average Bj${\o}$ntegaard delta bitrate gains of about 24% for spatial scalability and of about 21% for SNR scalability compared to simulcast coding with HEVC.