• Title/Summary/Keyword: Scalable Information

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An Efficient Dynamic Network Security Method based on Symmetric Block Cipher Algorithms (대칭적인 블록 암호화 알고리즘을 기반으로 한 효율적인 다이내믹 네트워크 보안 방법)

  • Song, Byoung-Ho;Yang, Sung-Ki;Bae, Sang-Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.4
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    • pp.169-175
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    • 2008
  • The existing block encryption algorithms have been designed for the encryption key value to be unchanged and applied to the round functions of each block. and enciphered. Therefore, it has such a weak point that the plaintext or encryption key could be easily exposed by differential cryptanalysis or linear cryptanalysis, both are the most powerful methods for decoding block encryption of a round repeating structure. Dynamic cipher has the property that the key-size, the number of round, and the plaintext-size are scalable simultaneously. Dynamic network is the unique network satisfying these characteristics among the networks for symmetric block ciphers. We analyze the strength of Dynamic network for meet-in-the-middle attack, linear cryptanalysis, and differential cryptanalysis. Also, In this paper we propose a new network called Dynamic network for symmetric block ciphers.

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A 1.8V 2-Gb/s SLVS Transmitter with 4-lane (4-lane을 가지는 1.8V 2-Gb/s SLVS 송신단)

  • Baek, Seung-Wuk;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.357-360
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    • 2013
  • A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

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The Study of Security Life Cycler Energy Service Platform or Universal Middleware (유니버설미들웨어상의 생명주기기반 보안에너지 서비스플랫폼 연구)

  • Lee, Hae-Jun;Hwang, Chi-Gon;Yoon, Chang-Pyo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.05a
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    • pp.291-293
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    • 2017
  • Security services that support electric energy service gateway require relatively high reliability. In particular, the application services that accompany communications and data are run organically. Each of the security services should support a secure service platform that supports a secure, scalable life cycle for existing services which should be extends security layer of Universal Middleware such as OSGi platform. In this convergence platform, it is the study of security transfer modular services that allow independent life cycle management of systems through Universal middleware. First, It is modular in terms of energy consumption service and data, enabling real-time operation, communications, remote management and applications. Second, the life cycle of the secure module to support the life cycle of secure, delete, start and updating of the security module by applying the security policy module layer concept. It is modular in terms of power generation and accountability, enabling us to distinguish between reliability and accountability in a large volume of data models in the smart grid, the service was intended to be standardized and applied to the security service platform.

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Directory Cache Coherence Scheme using the Number-Balanced Binary Tree (수 평형 이진트리를 이용한 디렉토리 캐쉬 일관성 유지 기법)

  • Seo, Dae-Wha
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.3
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    • pp.821-830
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    • 1997
  • The directory-based cache coherence scheme is an attractive approach to solve the caceh coherence problem in a large-scale shared-memory multiprocessor.However, the exsting directory-based schemes have some problens such as the enormous storage overhead for a directory, the long invalidation latency, the heavy network condes-tion, and the low scalability.For resolving these problems, we propose a new directroy- based caceh coherence scheme which is suitable for building scalable, shred-memory multiprocessors.In this scheme, each directory en-try ofr a given memory block is a number-balanced binaty tree(NBBT) stucture.The NBBT has several proper-ties to effciently maintain the directory for the cache consistency such that the shape is unique, the maximum depth is [log$_2$n], and the tree has the minimum number of leaf nodes among the binarry tree with n nodes.Therefore, this scheme can reduce the storage overhead, the network traffic, and the inbalidation latency and can ensutr the high- scalability the large-scale shared-memory multiprocessors.

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The Design and Implementation of Monitoring System for Grid Network (그리드 네트워크를 위한 모니터링 시스템의 설계 및 구현)

  • Ha, Ji-A;Ahn, Seon-Gjin;Chung, Jin-Wook;Hwang, Il-Sun;Kim, Kui-Nam;Kim, Dong-Kyun;Lee, Hyuk-Ro
    • The KIPS Transactions:PartC
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    • v.10C no.7
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    • pp.915-922
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    • 2003
  • The Grid is an infrastructure to connect heterogeneous resources that are scattered over areas with high-speed network and to cooperate with each other. To support Grid applications, network resources should be managed, since the network has to be safe and reliable. The Grid Monitoring Architecture Working Group (GMAWG) of the Global Grid Forum (GGF) proposed an effective architecture to be scalable across wide-area networks and encompass a large number of heterogeneous resources. In this paper, we describe the design and implementation of Grid network monitoring system based on the GMA for practical network management. By this system, network operations center can form a management system flexibly and scalably for Grid network.

A Linear Time Algorithm for Constructing a Sharable-Bandwidth Tree in Public-shared Network (공유 네트워크에서 공유대역폭 트리 구성을 위한 선형 시간 알고리즘)

  • Chong, Kyun-Rak
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.6
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    • pp.93-100
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    • 2012
  • In this paper we have proposed a linear time algorithm for solving the minimum sharable-bandwidth tree construction problem. The public-shared network is a user generated infrastructure on which a user can access the Internet and transfer data from any place via access points with sharable bandwidth. Recently, the idea of constructing the SVC video streaming delivery system on public-shared network has been proposed. To send video stream from the stream server to clients on public-shared network, a tree structure is constructed. The problem of constructing a tree structure to serve the video streaming requests by using minimum amount of sharable bandwidth has been shown to be NP-hard. The previously published algorithms for solving this problem are either unable to find solutions frequently or less efficient. The experimental results showed that our algorithm is excellent both in the success rate of finding solutions and in the quality of solutions.

DESIGN OF A HIGH-THROUGHPUT VITERBI DECODER (고속 전송을 위한 비터비 디코더 설계)

  • Kim, Tae-Jin;Lee, Chan-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.20-25
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    • 2005
  • A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

Performance Evaluation of Label Switching in ATM networks. (ATM 망에서의 레이블 스위칭 기법 성능 평가 및 분석)

  • 이수경;오경희;손홍세;송주석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.3B
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    • pp.437-445
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    • 2000
  • More advanced and demanding applications, like videoconferencing, video on demand. distributed computing etc., have been devised thanks to the availability of enhanced network feature. Network technologies need to be enhanced to support these applications and to cope with the increasing number of users. Increasing the availability of network resources is just not enough to achieve this goal; scalable network architecture. increased packet forwarding capabilities, a wider range of services are all additional requirements. MOLS (multiprotocol label Switching) is one of the new networking techniques under standardization in the scientific community. In this paper, we analyze the performance of label switching in ATM networks. Simulation tests were performed. In this simulation, we set a simple network configuration and used internet traffic traces from NLANR as input traffic sources. The simulation results and analysis will be helpful in utilizing the functions of ATM switching and IP routing.

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A Study of Core-Stateless Mechanism for Fair Bandwidth Allocation (대역 공평성 보장을 위한 Core-Stateless 기법 연구)

  • Kim, Hwa-Suk;Kim, Sang-Ha;Kim, Young-Bu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4C
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    • pp.343-355
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    • 2003
  • Fair bandwidth allocations at routers protect adaptive flows from non-adaptive ones and may simplify end-to end congestion control. However, traditional fair bandwidth allocation mechanisms, like Weighted Fair Queueing and Flow Random Early Drop, maintain state, manage buffera and perform packet scheduling on a per-flow basis. These mechanisms are more complex and less scalable than simple FIFO queueing when they are used in the interi or of a high-speed network. Recently, to overcome the implementation complexity problem and address the scalability and robustness, several fair bandwidth allocation mechanisms without per-flow state in the interior routers are proposed. Core-Stateless Fair Queueing and Rainbow Fair Queuing are approximates fair queueing in the core-stateless networks. In this paper, we proposed simple Layered Fair Queueing (SLFQ), another core-stateless mechanism to approximate fair bandwidth allocation without per-flow state. SLFQ use simple layered scheme for packet labeling and has simpler packet dropping algorithm than other core-stateless fair bandwidth allocation mechanisms. We presente simulations and evaluated the performance of SLFQ in comparison to other schemes. We also discussed other are as to which SLFQ is applicable.

Scalable Race Visualization for Debugging Message-Passing Programs (메시지전달 프로그램의 디버깅을 위한 경합의 확장적 시각화)

  • Park Mi-Young;Jun Yong-Kee
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.7
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    • pp.341-348
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    • 2005
  • Detecting unaffected race conditions is important for debugging message-passing programs effectively, because such races can influence other races to occur or not. The previous technique used in detecting unaffected races detects a race by halting the execution of a process at the receive event of the race that errors first in the process. However this technique does not guarantee that all of the detected races are unaffected, because halting the execution of processes does disconnect some chains of affects-relations among those races. Tn this paper. we improved the second pass algorithm of the previous technique by producing information about affects-relations of the races that occur first in each Process. Then we effectively visualize affect-relations among the races detected in each process. This visualization is effective in detecting visually unaffected races by simplifying affects-relations among the races which occur first In each Process.