• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.99-102
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• 2008

OFDM 시스템에서는 수신단의 샘플링 주파수가 정확하지 않을 경우 샘플링 주파수 옵셋으로 인한 ICI(Inter-Carrier Interference) 현상이 발생하여 수신 성능의 열화를 초래한다. 일반적으로 샘플링 주파수 옵셋의 추정은 연속된 2개의 OFDM 심볼의 파일럿 신호 또는 약속된 신호간의 상관을 통하여 수행된다. 본 논문에서는 주파수 영역에서 연속된 심볼들 간의 다양한 조합을 이용하여 샘플링 주파수 옵셋을 추정하고 그 성능을 비교한다. 이를 위해 각 방식을 DVB-T 시스템에 적용하여 모의실험을 수행한 결과와 기존 기법과의 성능을 비교 분석하였으며, 그 결과 AWGN 채널 환경에서 샘플링 주파수 옵셋 추정 성능을 향상시킬 수 있음을 확인하였다.

• ETRI Journal
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• v.29 no.5
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• pp.596-606
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• 2007

It is well known that an OFDM receiver is vulnerable to synchronization errors. Despite fine estimations used in the initial acquisition, there are still residual synchronization errors. Though these errors are very small, they severely degrade the bit error rate (BER) performance. In this paper, we propose a residual error elimination scheme for the digital OFDM baseband receiver aiming to improve the overall BER performance. Three improvements on existing schemes are made: a pilot-aided recursive algorithm for joint estimation of the residual carrier frequency and sampling time offsets; a delay-based timing error correction technique, which smoothly adjusts the incoming data stream without resampling disturbance; and a decision-directed channel gain update algorithm based on recursive least-squares criterion, which offers faster convergence and smaller error than the least-mean-squares algorithms. Simulation results show that the proposed scheme works well in the multipath channel, and its performance is close to that of an OFDM system with perfect synchronization parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1030-1038
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• 2013

The proposed Alamouti coded OFDM effectively cancels Inter Carrier Interference (ICI) due to frequency offset between distributed antennas. The conventional Alamouti coded OFDM schemes to mitigate ICI utilize N-point Inverse Fast Fourier Transform/Fast Fourier Transform (IFFT/FFT) operations for OFDM modulation and demodulation processes with total N subcarriers. However, the performance degrades because ICI is also repeated in N periods due to the property of N-point IFFT/FFT operation. In order to avoid this problem, null data are used at the subcarriers with large ICI and thus, data rate decreases. The proposed scheme employs 2N-point IFFT/FFT instead of N-point IFFT/FFT in order to increase sampling rate. By increasing sampling rate, the amount of interference significantly decreases because the period of ICI also increases. The proposed scheme increases the data rate and improves the performance by reducing amount of ICI and the number of null-data. Furthermore, the gain of the performance and data rate of the proposed scheme is significant with higher modulation such as 16-Quadarature Amplitude Modulation (QAM) or 64-QAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.16-23
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• 2009

A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.