• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2380-2386
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• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.7-14
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• 2012

A image quality is limited by a sample-and-hold circuit of the X-ray CMOS image sensor even though simple mos switch or bootstrapped clock circuit are used to get high quality sampled signal. Because distortion of sampled signal is produced by the charge injection from sample-and-hold circuit even using bootstrapped. This paper presents the 3D micro-inductor design methode in the CMOS process. Using this methode, it is possible to increase the ENOB (effective number of bit) through the use of micro-inductor which is calculated and designed in standard CMOS process in this paper. The ENOB is improved 0.7 bit from 17.64 bit to 18.34 bit without any circuit just by optimized inductor value resulting in verified simulation result. Because of this feature, micro-inductor methode suggested in this paper is able to adapt a mamography that is needed high resolution so that it help to decrease patients dose amount.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of the Korean Magnetics Society
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• v.15 no.6
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• pp.332-335
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• 2005

Output voltage of the flux-meter has always drift due to the input bias current of non-ideal operational amplifier. In this study we have employed a digital sample and hold amplifier which has no voltage drop to compensate drift of the flux-meter automatically. The drift of the developed flux-meter was smaller than $5{\times}10^{-8}\;Wb/s$ for the integration time constant of $RC=10^{-3}$ s.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.389-394
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• 2014

This paper presents the effect of a reflective force computed from a first-order-hold method on the stability of a haptic system. A haptic system is composed of a haptic device with a mass and a damper, a virtual spring, a sampler and a sample-and-hold. The boundary condition of the maximum virtual stiffness is analytically derived by using the Routh-Hurwitz criterion and the condition shows that the maximum virtual stiffness is proportional to the square root of the mass and the damper of a haptic device and also is inversely proportional to the sampling time to the power of three over two. The effectiveness of the derived condition is evaluated by the simulation. When the reflective forces are computed by using the first-order-hold method, the maximum available stiffness to guarantee the stability is increased several hundred times as large as when the zero-order-hold method is applied.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Journal of Magnetics
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• v.8 no.4
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• pp.160-163
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• 2003

In magnetic flux measurement, output voltage drift of electronic integrator is an essential problem. In this work, we have developed a new kind of Miller type integrator using a sample and hold amplifier. Input bias current was measured and this value was hold in the sample and hold amplifier, after that input bias current of Miller integrator was compensated automatically using the value which holds in the sample and hold amplifier. Developed flux-meter shows the drift of flux-meter are smaller than 10$^{-5}$ Wb/min in full scale of 10$^{-2}$, and we could also measure multi-channel magnetic flux simultaneously.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.239-247
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• 1996

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.27-33
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• 2016

This paper proposes a Low Noise Amplifier (LNA) with chopper stabilization technique with a sample-hold circuit. Chopper stabilization technique is effective in terms of reducing low frequency offset and flicker noise. Conventional chopper amplifier has a disadvantage in area because of using Low Pass Filter (LPF) for remove chopping spike. The proposed chopper amplifier employed sample and hold technique to decrease chopping spike instead of LPF that improves 36% in voltage damping and 11% in area.