• Title/Summary/Keyword: SW Optimization

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Assessment of Displacement and Axial Force of Earth Retaining Wall at Each Excavation Step Using Direct Algorithm Back Analysis (직접알고리즘 역해석 기법을 이용한 굴착단계별 흙막이 가시설 변위 및 축력의 적정성 평가)

  • So-Ra Kang;Je-Seok Jeon;Yeong-Jin Lee;Jun-Seok Lee;Kang-Il Lee
    • Journal of the Korean Geosynthetics Society
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    • v.23 no.1
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    • pp.27-37
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    • 2024
  • In this study, direct algorithm-based back analysis was utilized to perform back analysis on two actual earth retaining wall fields, which was then compared with genetic algorithm-based method to evaluate the suitability of the back analysis. Additionally, in order to propose effective utilization methods of the program, the measurement data, as the input for the back analysis, was varied for each excavation step, and the applicability of the back analysis results(displacement, axial force) was examined. The research findings indicate that both direct algorithm and genetic algorithm show high applicability; however, the optimization for this program is better predicted by the direct algorithm. Moreover, in order to effectively use the back analysis program employing the direct algorithm, it was evaluated that relatively accurate prediction of the earth retaining wall behavior could be achieved by inputting measurement data from the 7th excavation step for fields with final excavation steps ranging from 8 to 11.

Intelligent Traffic Prediction by Multi-sensor Fusion using Multi-threaded Machine Learning

  • Aung, Swe Sw;Nagayama, Itaru;Tamaki, Shiro
    • IEIE Transactions on Smart Processing and Computing
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    • v.5 no.6
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    • pp.430-439
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    • 2016
  • Estimation and analysis of traffic jams plays a vital role in an intelligent transportation system and advances safety in the transportation system as well as mobility and optimization of environmental impact. For these reasons, many researchers currently mainly focus on the brilliant machine learning-based prediction approaches for traffic prediction systems. This paper primarily addresses the analysis and comparison of prediction accuracy between two machine learning algorithms: Naïve Bayes and K-Nearest Neighbor (K-NN). Based on the fact that optimized estimation accuracy of these methods mainly depends on a large amount of recounted data and that they require much time to compute the same function heuristically for each action, we propose an approach that applies multi-threading to these heuristic methods. It is obvious that the greater the amount of historical data, the more processing time is necessary. For a real-time system, operational response time is vital, and the proposed system also focuses on the time complexity cost as well as computational complexity. It is experimentally confirmed that K-NN does much better than Naïve Bayes, not only in prediction accuracy but also in processing time. Multi-threading-based K-NN could compute four times faster than classical K-NN, whereas multi-threading-based Naïve Bayes could process only twice as fast as classical Bayes.

EDISON Co-rotational Plane Beam Transient analysis solver를 이용한 위험 Gust profile 역-추적 알고리즘 개발

  • Jeong, Ji-Seop;Kim, Se-Il;Sin, Sang-Jun
    • Proceeding of EDISON Challenge
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    • 2017.03a
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    • pp.259-269
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    • 2017
  • Gust load is a very important load factor in designing various structures of an aircraft and judging its stability. This is because the blast effect on the aircraft in operation increases the risk of damage to the structure of the aircraft and causes a negative impact such as shortening the fatigue life by generating vibration. Particularly in the case of wing, a change in angle of attack is caused by gust load, and an additional lift acts on the wing, thereby being exposed to various excitational environments. Severe structural damage to the aircraft may occur if the natural frequencies of the aircraft wing are close to or coincident with the frequencies of the gust load applied to the wing. Recent trends of research include flight dynamics analysis considering discontinuous gusts or structural optimization of the blades under gust load. A number of studies have been conducted to interpret gust load response in consideration of irregularities in gusts. In this paper, we tried to imagine the situation of the aircraft subjected to the gust load as realistic as possible, and proposed an algorithm to track back the critical gust profile according to given aircraft characteristics from the viewpoint of preliminary engineering prediction.

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Optimization of Honeycomb Spoke in Non-pneumatic Tire (비공기압 타이어에 사용되는 Honeycomb Spoke의 최적화)

  • Lee, Jinwook;Jang, Inhwan;Han, Gyumo
    • Proceeding of EDISON Challenge
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    • 2017.03a
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    • pp.204-215
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    • 2017
  • Unlike existing pneumatic tire, NPT(Non-Pneumatic Tire) is a tire replacing air pressure with spokes. NPT has no problem of punk which pneumatic tire has and doesn't need to maintain air pressure. Also it can be used in space where temperature change sharply. In this regard, NPT are attracting attention as next-generation wheels. For optimizing Honeycomb structure, we applied the load to various Honeycomb structure which forms NPT, performed FEM(finite element analysis) using Edison and compared each results.

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Development of Sensor Placement Optimization Algorithm for Smart Container Control (스마트 컨테이너 제어를 위한 센서 위치 최적화 알고리즘 개발)

  • Kim, Jeong-ho;Jeon, Byeong-jin;Park, Byeong-jun;Lee, Sang-jin;Im, Hyeon-seok;Kim, Hyung-hoon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2022.11a
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    • pp.1047-1049
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    • 2022
  • 스마트 컨테이너 제어를 위해서는 컨테이너 내부에 센서가 필요하나, 센서의 개수가 증가하면 비용 및 시스템 부하가 증가한다. 본 연구에서는 CFD(Computational Fluid Dynamics)를 이용하여 얻은 컨테이너 내부 온도 데이터와 센서 위치 최적화 알고리즘을 이용하여 컨테이너 내부 모니터링을 위한 최적의 센서 위치 결정 방법론을 제시한다. CFD 상용 SW로 컨테이너 내·외부 상황을 가정하여 내부 온도 데이터를 추출하고, 이를 바탕으로 내부 상태를 대표하는 공간들을 구분한다. 컨테이너 내벽에 부착된 센서가 탐지할 수 있는 능력을 탐지 거리 및 각도의 수식들로 나타내어 각 수식을 조합하여 센서의 탐지 능력을 수치화하고, 이 수치에 따라 균등하게 분포된 센서 위치 후보군 중, 선별된 공간을 탐지하는 센서 위치를 최적화하여 효율적인 컨테이너 제어를 위한 여건을 마련한다.

Fruit price prediction study using artificial intelligence (인공지능을 이용한 과일 가격 예측 모델 연구)

  • Im, Jin-mo;Kim, Weol-Youg;Byoun, Woo-Jin;Shin, Seung-Jung
    • The Journal of the Convergence on Culture Technology
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    • v.4 no.2
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    • pp.197-204
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    • 2018
  • One of the hottest issues in our 21st century is AI. Just as the automation of manual labor has been achieved through the Industrial Revolution in the agricultural society, the intelligence information society has come through the SW Revolution in the information society. With the advent of Google 'Alpha Go', the computer has learned and predicted its own machine learning, and now the time has come for the computer to surpass the human, even to the world of Baduk, in other words, the computer. Machine learning ML (machine learning) is a field of artificial intelligence. Machine learning ML (machine learning) is a field of artificial intelligence, which means that AI technology is developed to allow the computer to learn by itself. The time has come when computers are beyond human beings. Many companies use machine learning, for example, to keep learning images on Facebook, and then telling them who they are. We also used a neural network to build an efficient energy usage model for Google's data center optimization. As another example, Microsoft's real-time interpretation model is a more sophisticated translation model as the language-related input data increases through translation learning. As machine learning has been increasingly used in many fields, we have to jump into the AI industry to move forward in our 21st century society.

Performance Analysis of Cache and Internal Memory of a High Performance DSP for an Optimal Implementation of Motion Picture Encoder (고성능 DSP에서 동영상 인코더의 최적화 구현을 위한 캐쉬 및 내부 메모리 성능 분석)

  • Lim, Se-Hun;Chung, Sun-Tae
    • The Journal of the Korea Contents Association
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    • v.8 no.5
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    • pp.72-81
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    • 2008
  • High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

Design Process Suggestion of Vibrotactile Interface applying Haptic Perception Factor Analysis (햅틱 인지 요인 분석을 적용한 진동 촉감 인터페이스 설계 프로세스 제안)

  • Heo, Yong-Hae;Kim, Seung-Hee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.5
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    • pp.79-87
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    • 2021
  • This study suggests a design process for vibrotactile interface that can apply haptic perception factors reflecting human tactile mechanisms. This process consists of 4 stages: the haptic sense requirement analysis stage, the haptic element analysis stage, the haptic perception factor analysis stage, the haptic requirement detailed design, and the prototype implementation stage. The advantage of this design process is that unnecessary tasks can be excluded in deriving and implementing user requirements, by applying haptic perception factor analysis, and the biggest feature is that research results on ergonomic mechanisms can be reflected in the haptic design, completes prototype development simultaneously while determining the haptic requirements statement by performing user evaluation, usability testing, and haptic feature optimization tasks simultaneously. This design process includes all stages from user requirements to haptic function detailed design and prototype implementation, so it is expected that general developers who lack expertise in haptic will also be able to design user-centered designs, enabling design and implementation of haptic functions at a certain level.

Development of a Digital Platform for Carbon Neutrality in the Ocean (해양 탄소중립 실현을 위한 디지털 플랫폼 개발)

  • Young-Hoon Yang;Jin-Hyoung Park;Deuk-Jae Cho
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • 2022.06a
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    • pp.317-318
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    • 2022
  • In accordance with global decarbonization, optimization and productivity improvement using digital twin are being sought, and software development for optimizing ship and marine energy operation is accelerating by selecting digital twin as a future core technology. In order to reduce the operating cost of ships and strengthen the competitiveness of the shipbuilding industry due to the international strengthening of regulations on carbon emissions, it is necessary to predict the carbon emission of ships in advance and provide a carbon reduction operation solution. A plan was carried out for the development of open digital platform technology and the establishment of an environment to support the securing of carbon transparency of the ship and offshore system.

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MP3 Encoder Chip Design Based on HW/SW Co-Design (하드웨어 소프트웨어 Co-Design을 통한 MP3 부호화 칩 설계)

  • Park Jong-In;Park Ju Sung;Kim Tae-Hoon
    • The Journal of the Acoustical Society of Korea
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    • v.25 no.2
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    • pp.61-71
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    • 2006
  • An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.