• Title/Summary/Keyword: SRAM Memory

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A Study on the Development of Semi-automated Analog Cell Compiler for MML Library (MML(merged memory logic) 라이브러리 구축을 위한 반자동 아날로그 컴파일러 개발에 관한 연구)

  • 최문석;송병근곽계달
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.695-698
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    • 1998
  • Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.

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Study on annealing of $Cr/Co/Al-O_x/Co/Ni-Fe$ Magnetic Tunneling junctions

  • 이종윤;전동민;박진우;윤성용;백형기;서수정
    • Proceedings of the Korean Magnestics Society Conference
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    • 2002.12a
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    • pp.72-73
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    • 2002
  • MR(Magnetoresistance)현상이란 인가된 자장에 의해 저항이 변하는 현상이다. 이 현상은 여러 측면에서 연구되고 있고 그 중 TMR(Tunneling Magnetoresistance)현상은 sensor, head, memory device의 적용에 대한 연구가 진행 중에 있다. 특히 memory 소자 측면에서 MRAM은 현재 사용되고 있는 DRAM이나 SRAM들과는 달리 비휘발성과 기록밀도의 고집적 등 많은 장점을 갖는 소자로써 연구되고 있다. (중략)

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Scratchpad-Memory Management Using NUMA Infrastructure on Linux (Linux 상에서 NUMA 지원을 응용한 스크래치 패드 메모리 관리방법)

  • Park, Byung-Hun;Seo, Dae-Wha
    • Proceedings of the Korea Information Processing Society Conference
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    • 2009.11a
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    • pp.41-42
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    • 2009
  • 현재 많은 임베디드 SoC(System-On-Chip)에는 캐시 메모리의 단점을 보완하기 위해 온-칩(On-Chip) SRAM, 즉, SPM(Scratchpad Memory)를 내장하고 있으며 SPM은 그 특성상 캐시 메모리와 달리 소프트웨어가 직접 관리해야 한다. 본 논문에서는 NUMA를 지원하는 Linux 상에서 이식성이 높으면서 단순하게 구현할 수 있는 SPM 관리 방법을 제안한다.

A design of BIST circuit and BICS for efficient ULSI memory testing (초 고집적 메모리의 효율적인 테스트를 위한 BIST 회로와 BICS의 설계)

  • 김대익;전병실
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.8
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    • pp.8-21
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    • 1997
  • In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

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Lifetime Maximization of Wireless Video Sensor Network Node by Dynamically Resizing Communication Buffer

  • Choi, Kang-Woo;Yi, Kang;Kyung, Chong Min
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.10
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    • pp.5149-5167
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    • 2017
  • Reducing energy consumption in a wireless video sensor network (WVSN) is a crucial problem because of the high video data volume and severe energy constraints of battery-powered WVSN nodes. In this paper, we present an adaptive dynamic resizing approach for a SRAM communication buffer in a WVSN node in order to reduce the energy consumption and thereby, to maximize the lifetime of the WVSN nodes. To reduce the power consumption of the communication part, which is typically the most energy-consuming component in the WVSN nodes, the radio needs to remain turned off during the data buffer-filling period as well as idle period. As the radio ON/OFF transition incurs extra energy consumption, we need to reduce the ON/OFF transition frequency, which requires a large-sized buffer. However, a large-sized SRAM buffer results in more energy consumption because SRAM power consumption is proportional to the memory size. We can dynamically adjust any active buffer memory size by utilizing a power-gating technique to reflect the optimal control on the buffer size. This paper aims at finding the optimal buffer size, based on the trade-off between the respective energy consumption ratios of the communication buffer and the radio part, respectively. We derive a formula showing the relationship between control variables, including active buffer size and total energy consumption, to mathematically determine the optimal buffer size for any given conditions to minimize total energy consumption. Simulation results show that the overall energy reduction, using our approach, is up to 40.48% (26.96% on average) compared to the conventional wireless communication scheme. In addition, the lifetime of the WVSN node has been extended by 22.17% on average, compared to the existing approaches.

A Parallel Hardware Architecture for H.264/AVC Deblocking Filter (H.264/AVC를 위한 블록현상 제거필터의 병렬 하드웨어 구조)

  • Jeong, Yong-Jin;Kim, Hyun-Jip
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.45-53
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    • 2006
  • In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

  • Sandip, Bhattacharya;Mohammed Imran Hussain;John Ajayan;Shubham Tayal;Louis Maria Irudaya Leo Joseph;Sreedhar Kollem;Usha Desai;Syed Musthak Ahmed;Ravichander Janapati
    • ETRI Journal
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    • v.45 no.5
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    • pp.910-921
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    • 2023
  • In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs

  • Panth, Shreepad;Samal, Sandeep;Yu, Yun Seop;Lim, Sung Kyu
    • Journal of information and communication convergence engineering
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    • v.12 no.3
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    • pp.186-192
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    • 2014
  • Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

Design of Electronic Control Unit for Parking Assist System (주차 보조 시스템을 위한 ECU 설계)

  • Choi, Jin-Hyuk;Lee, Seongsoo
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1172-1175
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    • 2020
  • Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

FPGA Design and SoC Implementation of Constant-Amplitude Multicode Bi-Orthogonal Modulation (정진폭 다중 부호 이진 직교 변복조기의 FPGA 설계 및 SoC 구현)

  • Hong, Dae-Ki;Kim, Yong-Seong;Kim, Sun-Hee;Cho, Jin-Woong;Kang, Sung-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.11C
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    • pp.1102-1110
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    • 2007
  • In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).