• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.179-184
• /
• 2023

We propose the modeling methodology of CMOS inverter made of LTPO TFT using a machine learning. LTPO can achieve advantages of LTPS TFT with high electron mobility as a driving TFT and IGZO TFT with low off-current as a switching TFT. However, since the unified model of both LTPS and IGZO TFTs is still lacking, it is necessary to develop a SPICE-compatible compact model to simulate the LTPO current-voltage characteristics. In this work, a generic framework for combining the existing formula of I-V characteristics with artificial neural network is presented. The weight and bias values of ANN for LTPS and IGZO TFTs is obtained and implemented into PSPICE circuit simulator to predict CMOS inverter. This methodology enables efficient modeling for predicting LTPO TFT circuit characteristics.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.10
• /
• pp.1317-1326
• /
• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.397-404
• /
• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• Proceedings of the KIPE Conference
• /
• 2000.07a
• /
• pp.1-5
• /
• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.94-100
• /
• 1994

By using the RAPHAEL 3D inductance calculation program RI3, the PGA package inductance values of INTEL i486 microprocessor have been extracted. The lead frame layouts are drawn using the mentor Boardstation and the output files are converted into the RI3 program input format of RAPHAEL. The power and ground planes of the PGA package are modeled y grid-line structures of single bars. The capacitance valuse of signal lines have been clalculated by using the RAPHAEL 2D/3D capacitance extraction program. The extraced L, C, R values have been converted into the SPICE netlist formats with lumped circuit model for future use in the signal ingegrity analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.2
• /
• pp.28-28
• /
• 2001

능동제어형 전계방출 디스플레이의 전자공급원으로서 능동제어형 전계 에미터 어레이의 회로모델이 제안되었다. 능동제어형 전계 에미터 어레이는 전계방출을 안정화시키고 저전력구동을 위한 수소화 된 비정질 실리콘 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이로 구성되었고 같은 유리기판 위에 제작되었다. 비정질 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이의 전기적 특성으로부터 추출된 기본 모델 변수는 제안된 능동제어형 전계 에미터 어레이 회로모델에 입력되었고 SPICE 회로 시뮬레이터를 사용하여 특성을 분석하였다. 제작된 소자의 측정값과 DC 시뮬레이션 결과를 비교한 결과 두 값이 상당히 일치함으로써 등가회로 모델의 정확성을 확인하였다. 또한 제작된 소자의 transient 시뮬레이션 결과 전계 에미터 어레이의 게이트 커패시턴스와 TFT의 구동능력이 반응시간에 가장 크게 영향을 끼치고 있음을 확인하였다. 제작된 능동제어형 전계방출 에미터 어레이는 pulse width modulation으로 구동하는 경우 15㎲의 반응시간을 얻었고 이 값으로는 4bit/color의 계조(gray scale)표현이 가능하였다.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.9-12
• /
• 2000

InP/lnGaAs heterojunciton phototransistors (HPTs) with transparent emitter contacts were fabricated and characterized. Indium Tin Oxide was RF sputtered for the emitter contacts. By comparison with InP/InGaAs HBTs, the dc characteristics of InP/lnGaAs HPTs demonstrated offset voltage due to ITO emitter contacts and similar common emitter current gain. The model parameters were extracted and a simple SPICE simulations were performed.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.180-187
• /
• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2002.11a
• /
• pp.324-327
• /
• 2002

For the characterization of arbitrary shaped printed circuit board, lossy transmission line grid model based on SPICE netlist and analytical plane model based on the segmentation method are proposed in this paper. Two methods are compared with an arbitrary shaped power/ground plane. Furthermore, design considerations for the complete power distribution network structure are discussed to ensure the maximum value of the PDN impedance is low enough across the desired frequency range and to guide decoupling capacitor selection.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10d
• /
• pp.4-6
• /
• 2002

최근 소프트웨어 산업에서는 개발 기간의 지연, 비용 증대와 같은 위험관리를 하기 위한 방법으로, SPI 전략이 활발히 진행되고 있다. 사실표준인 CMM이나 국제표준인 SPICE 등이 SPI의 참조적인 모델로 사용된다. 그러나 이들 모델은 특정환경을 가진 소프트웨어 개발 조직에 대한 품질 개선을 위해서 필요한 구체적인 개선 절차와 방법을 기술하고있지 않다. 특히 SPI를 위해서 SPA가 선행되는 경우가 많은데, 효율적인 SPA를 위해서는 심사절차에 대한 정형화가 필요하며 이를 통하여 심사의 일관성을 유지할 수가 있다. 본 논문에서는 심사의 정형화를 위해 SPA의 각 단계들을 UML을 사용하여 표현하고, 모델의 신뢰성을 ISO/IEC 9126의 6가지 품질 특성의 테두리 안에서 검증하고자 한다. 또한 결함들(Defect)간에 연관성을 분석하여, SPA의 등급평가 절차에서 사용되도록 제안한다.