• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.535-541
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• 2000

In this paper, we analyzed the characteristics of schottky junction to develop the voltage swing of ISL, and simulated the characteristics with the programs at this junctions. Simulation programs for analytic characteristics are the SUPREM V, SPICE, Medichi, Matlab. The schottky junction is rectifier contact between platinum silicide and silicon, the characteristics with programs has simulated the same conditions. The analytic parameters were the turn-on voltage, saturation current, ideality factor in forward bias, and has shown the results of breakdown voltage between actual characteristics and simulation characteristics in reverse bias. As a result, th forward turn-on voltage, reverse breakdown voltage, barrier height were decreased but saturation current and ideality factor were increased by substrates increased concentration variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.2
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• pp.1-7
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• 1997

커패시터 방전회로의 제작 및 시험을 위해서는 고가의 비용과 위험요소가 내재되어 있으며 특히 고전력 응용을 위해서는 이러한 요소는 더욱 커지게 된다. 그 대체방법으로는 컴퓨터를 이용하여 이 회로의 동작을 모델링하고 시뮬레이션하는 것이다. 본 연구에서는 커패시터 방전 임펄스 착자가 착아 요크 시스템을 위한 SPICE 모델을 개발하고 시뮬레이션 결과를 실제 시스템의 측정치와 비교하였다. 또한 착자기 시스템의 방전회로를 위한 온도산정방법을 제안하였다. 특히 임펄스 착자기의 방전회로의 온도산정은 착자회로 설계의 중요한 지침이 되므로 극히 중요하다. 본 연구에 이용된 착자기는 저손실 유입 커패시터이며, 최대 1200[V]의 충전이 가능하다. 이러한 착자 모델의 개발을 통하여 고임펄스 방전 회로의 설계 및 개발에 소요되는 시간 및 비용을 절약하는데 크게 기여할 것이다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1560-1563
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• 1987

This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.310-312
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• 1994

A partial shunt regulator (PSR) which is the power regulator of KOREASAT is modeled. The modeling of the PSR consist of solar array, power circuit, controller. and load models. To realize simple structure. a voltage source of the PSR controller is used the output voltage of the PSR. The model of the PSR has very complex structure with two additional coupled feedback loops. The complex model is simplified to a simple meaningful model with only main feedback control loop. The proposed model is compared to a PSR model with DC voltage source at the PSR controller. The proposed PSR model is verified by comparing the model with SPICE simulation for small signal analysis.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.922-924
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• 1995

The modeling of accurate timing in storage elements of ASIC cell library was studied. The propagation delay time of clock signal affects the critical time and this can cause malfunction in the chip designed in synchronous. In this paper, an analysis on the effect of input slope of clock signal in timing modeling were carried out. For the first time, in ASIC design, the design guides that can be used in both $0.6{\mu}M$ and $0.8{\mu}m$ design rule were offered, reducing the run time of SPICE and the time of cell library development.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1098-1100
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• 1993

In this paper, We found the thermal characterstic of impulsed magnetizing fixture system through the SPICE modeling and investigated the applied possibility in application aspects. As the detailed thermal characteristic of magnetizing fixure can be obtained, the efficient design of the magnetizing fixture which produce desired magnet will be possible using our thermal modeling. The purpose of this work is to compute the temperature increasing for different magnetizing conditions. The method uses multi-lumped model with equivalent thermal resistance and thermal capacitance. The model ing and experimental results are in close agreement.

• Journal of electromagnetic engineering and science
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• v.13 no.1
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• pp.54-61
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• 2013

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.