• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.270-274
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• 2011

This paper presents a parameterized simulation program with integrated circuit emphasis (SPICE) model of a two-level microbolometer based on negative-temperature-coefficient thin films, such as vanadium oxide or amorphous silicon. The proposed modeling begins from the electric-thermal analogy and is realized on the SPICE modeling environment. The model consists of parametric components whose parameters are material properties and physical dimensions, and can be used for the fast design study, as well as for the co-design with the readout integrated circuit. The developed model was verified by comparing the obtained results with those from finite element method simulations for three design cases. The thermal conductance and the thermal capacity, key performance parameters of a microbolometer, showed the average difference of only 4.77% and 8.65%, respectively.

• 전자공학회논문지A
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• 제31A권1호
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• pp.39-47
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• 1994

The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

• 한국전기전자재료학회논문지
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• 제28권3호
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• pp.154-159
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• 2015

In this paper, we propose a numerical method to model temperature dependent threshold voltage shift observed in metal oxide thin-film transistors (TFTs). The proposed model is then implemented in AIM-SPICE circuit simulation tool. The proposed method consists of modeling the well-known stretched-exponential time dependent threshold voltage shift and their temperature dependent coefficients. The outputs from AIM-SPICE tool and the stretched-exponential model at different temperatures in the literature are compared and they show a good agreement. Since metal oxide TFTs are the promising candidate for flat panel displays, the proposed method will be a good stepping stone to help enhance reliability of fast-evolving display circuits.

• 조명전기설비학회논문지
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• 제18권4호
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• pp.8-14
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• 2004

본 논문에서는 승압형 컨버터를 사용한 400(W) 고압나트륨 램프용 전자식 안정기 역률 보상회로를 설계하였다. 제안된 승압형 컨버터 회로에서 역률 보상 소자의 값을 이론적으로 계산하고 IsSPICE를 이용하여 시뮬레이션을 수행하였으며, 시뮬레이션 결과를 검증하기 위해 설계방법에 따라 전자식 안정기를 제작하여 실험하였다. 실험에 의한 역률 보상회로의 제반특성은 시뮬레이션 결과와 거의 일치하였다. 실험결과 출력 400(W)에서 역률 99.3(%)의 성과를 나타내었다.

• 조명전기설비학회논문지
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• 제18권5호
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• pp.27-34
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• 2004

본 논문에서는 half-bridge inverter를 이용하여 400[W] 고압나트륨 램프용 전자식 안정기를 설계하였다. 제안된 등가 LC 직렬 공진회로에서 인덕터와 커패시터의 값을 이론적으로 계산하고, LC 직렬 half-bridge 회로에 대한 IsSPICE 시뮬레이션을 수행하였다. 계산결과를 검증하기 위해 전자식 안정기를 설계 제작하여 실험을 수행하였다. 실험에 의한 전자식 안정기의 제반특성은 시뮬레이션 결과와 대단히 유사하였다. 실험결과 출력전압 400[W]에서 역률 99.3[%], 전류 전고조파 10.01[%], 램프효율 119[lm/W]의 좋은 성과를 나타내었다.

• 센서학회지
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• 제24권5호
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• 전기학회논문지
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• 제60권12호
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• pp.2281-2285
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• 2011

An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.498-500
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• 2006

본 논문에서는 SMC(Soft Magnetic Composit)의 특성이 고려된 구동시스템에 대한 특성 분석을 실시하였다. SMC는 기존의 전기강판과는 다른 자기적 특성으로 인해 기존 전기강판을 구동하는 시스템과 다른 특성을 지닌다. 본 논문은 이러한 SMC의 특성을 고려하기 위해서 FEM을 통해서 모터의 특성을 고려하였고, 인버터의 특성을 고려하기 위해서 Spice를 이용하여 FEM과 Spice의 연성해석을 통해 자기적 특성이 다른 모터의 구동 시스템에 대한 해석을 실시하였다.

• 한국통신학회논문지
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• 제24권12A호
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• pp.1985-1991
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• 1999

본 논문은 HANbit ACE64 ATM 교환기 시스템의 데이터 경로인 IMI(Inter Module Path)에 사용되는 고속 전송선로인 Twinax 케이블을 two-port lumped Spice-network 모델로 구현하기 위해 lumped 네트워크 요소와 수학적 함수를 사용하여 개발하였다. 사용된 요소들은 저항성분과 주파수의존 전압제어 소스로 구성되어 있고 Hspice 수학적 함수인 FREQ, DELAY, POLY를 사용하여 구현하였다. 구현된 모델을 사용하여 케이블 길이와 종류에 따른 각종 노이즈 분석을 실시하여 그 특성을 비교 분석하였다.

• Journal of information and communication convergence engineering
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• 제19권4호
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.