• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.11-21
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• 1997

The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.

• Proceedings of the Safety Management and Science Conference
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• 2001.05a
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• pp.59-66
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• 2001

본 연구는 8단계 소프트웨어 프로세스 모델을 제시하고 그 중 중요한 역할을 수행하는 SCM 프로세스를 소개한다. 끝으로 소프트웨어 프로세스개선 모델인 CMM, SPICE, IS0/IEC 12207, ISO 9000-3을 소개한다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.47-50
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• 2000

DC Gummel-Poon SPICE model parameter extraction program has been implemented. This program extracts the parameters from measured data using Levenberg-Marquardt algorithm. Measured data consist of forward and reverse Gummel plot, forward and reverse output characteristics and RE and RC measurements.

• Proceedings of the Korean Geotechical Society Conference
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• 2003.03a
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• pp.203-210
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• 2003

격자망식 전선배치에 의한 전기비저항 측정기법을 이용한 침출수 누출감지시스템을 개발하여 그 적용성을 평가하기 위하여 현장모형시험을 수행하였다. 현장모형시험을 수행한 결과 침출수 누출지점에서 전기비저항이 크게 감소하여 누출지점을 정확하게 감지할 수 있었다. 격자망식 전선배치에 의한 전기회로적인 효과로 인하여 전기비저항이 감소된 지점과 동일 전선상에 연결된 다른 센서에서의 측정값도 다소 감소하는 경향을 나타내었다. 이를 보정하기 위하여 P-SPICE를 이용하여 전기회로 시뮬레이션을 수행하여 전기회로 효과를 정량적으로 평가하였다 P-SPICE 시뮬레이션의 결과를 토대로 보정계수를 도출하여 현장모형시험결과를 보정하였으며, 보정된 겉과에 의하면 전기회로적 특성에 의한 영향을 효과적으로 제거되어 누출지점에서의 전기비저항 감소가 명확하게 나타났다.

• Biomedical Science Letters
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• v.16 no.1
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• pp.33-38
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• 2010

Culinary herbs and spices have received much attention since they contain high concentrations of bioactive ingredients for antioxidant and anti-inflammatory activities. Protection effect of the herb and spice against acute alcohol consumption has been investigated using zebrafish as a vertebrate model. During 30 days bathed in water containing 1% Et-OH and the designated herb or spice, the survival rate of the Et-OH group was decreased sharply (up to 20% at 10 days). The cinnamon-fed group showed the highest and longer survival rate up to 80% up to for 30 days under the presence of Et-OH, while clove-fed group showed 40% survival rate for 25 days. Et-OH group serum exhibited the weakest antioxidant ability from ferric ion removal ability (FRA) assay; FRA ability was increased in the cinnamon-fed group up to 414%, while the clove and laurel group increased 256% and 309%, respectively. Histologic observation and Oil-red O staining showed hepatic tissue damage was severe in the Et-OH group. The cinnamon- or clove-fed group showed much ameliorated hepatic tissue morphology with minimized steatosis. The cinnamon- or clove-fed group showed lower serum GOT and GPT levels than the Et-OH group. Among hepatic tissue extract, the clove-fed group exhibited the lowest level of GOT and GPT. These results suggest that consumption of cinnamon and clove might be beneficial to attenuate progress of acute fatty liver change by alcohol consumption.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.1
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• pp.49-58
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• 1998

In this paper, a new equivalent circuit model for quantum-well laser diode (LD) is proposed. The model includes carrier transport effects in the SCH region, and rprovides, in a stable and accurate manner, large-and small-signal responses of laser diode output power as function of injected currents. SPICE simulation was performed using the circuit model and results are presented for L-I characteristics, pulse and frequency responses under various conditions. It is expencted that the new equaivalent circuit model will find useful applications for designing and analyzing OEIC, LD driver circuits, and LD packaging.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• Knowledge Management Research
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• v.23 no.2
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• pp.61-82
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• 2022

Metaverse is a combination of Meta and Universe, which refers to a world in which users or avatars engage in social, economic, and cultural activities. This study attempted to compare the four worldviews proposed by the Acceleration Studies Foundation (ASF) based on the five evaluation factors of SPICE, which are factors for promoting customer experience. 227 samples were used in the analysis, and as a result, seamlessness was the highest in augmented reality, interoperability in lifelogging, presence in the mirror world, and concurrence in virtual reality. This study is meaningful in that it presents a model design plan according to the classification of the metaverse platform and the worldview, and presents detailed strategic directions to existing metaverse platform operators or new entrants.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.887-896
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• 2002

Based on SPICE (Software Process Improvement and Capability dEtermination) evaluation model, SPIRE (Software Process Improvement in Regions of Europe) is developed and published as a process improvement model for small and medium size organizations. However, practical selection guidelines or mapping rules between business goals and software processes do not exist within SPIRE. This research aims to construct an objective reference mapping table between business goals and software processes, and to propose a process selection method using the mapping table. The mapping table is constructed by the convergence of domestic software process experts' opinions using Delphi techniques. In the suggested process selection method, target processes are selected using the intuition of project participants or project managers as well as the reference mapping table. The feasibility of the proposed selection method has been reviewed by applying to two small software companies. Using the reference mapping table, we could select key processes which were passed over by project managers.