• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1132-1133
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• 2006

The approach, for ensuring the quality and safety of a railway software can be considered with two points of views seeing from products, and from processes. The process point of view is to validate maturity of the organizations in accordance to the judging processes of organizations, which are specified by CMMI(Capability Maturity Model Integration) or SPICE(Software Process Improvement and Capability dEtermination : ISO/IEC15504). In this paper, we are trying to find approaches to estimate the maturity of manufacturer and assessment organization in the railway system.

• Journal of the Korean Operations Research and Management Science Society
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• v.31 no.1
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• pp.37-53
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• 2006

SPI (Software Process Improvement) activities have been considered one of the crucial approaches to achieve high quality, productivity and timely delivery of software products and services. The basic premise of SPI model is that higher maturity levels lead to better performance. In this research, the relationships between SPI results and performance were empirically investigated with Korean software companies. CMM key process areas were categorized into two dimensions, 'Process Implementation' and 'Quantitative Management'. The relationship between process implementation and performance was significant, but the relationship between quantitative management and performance was insignificant. The control variable, size of OU(Organizational Unit), did not have significant impact on the relation ships between SPI activities and OU performance.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1025-1026
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• 2006

The approach, for ensuring the quality and safety of a railway software can be considered with two points of views seeing from products, and from processes. The process point of view is to validate maturity of the organizations in accordance to the judging processes of organizations, which are specified by CMMI(Capability Maturity Model Integration) or SPICE(Software Process Improvement and Capability dEtermination : ISO/IEC15504). In this paper, we are trying to find approaches to estimate the maturity of manufacturer and assessment organization in the railway system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.768-776
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• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.167-170
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• 2000

This paper describes a novel multi-operand radix-2 signed-digit(SD) adder. The novel multi-operand addition algorithm can eliminate carry propagation chain by dividing the input operands into even place part and odd place part, and adding them each. The multi-operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary method of SD adder binary tree. A hardware model for proposed adder is shown which is implemented by the current-mode MOSFET circuit technology. Simulations have been made by SPICE in order to verify the function of the proposed circuit.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.612-614
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• 1998

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

• Proceedings of the Optical Society of Korea Conference
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• 2006.07a
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• pp.427-428
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• 2006

LED(Light-Emitting Diode)내에서의 전류 분포를 계산하기 위한 SPICE 기반의 3차원 회로 모델을 개발하였다. 이 모델은 고전압, 고전류에서 구동되는 고휘도 LED의 전류 밀집(current crowding) 현상을 최소화하기 위한 설계 최적화에 이용할 수 있다. 본 논문에서는 $GaN/Al_2O_3$ 고휘도 청색 LED 내에서의 전류 분포를 분석하여 전극 설계를 최적화하기 위한 연구를 수행하였다.

• ETRI Journal
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• v.43 no.4
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• pp.717-727
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• 2021

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current bestperforming techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.285-288
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• 2021

4차 산업혁명의 출현과 함께 스마트공장, 스마트시티, 스마트러닝 등이 등장하면서 스마트 물관리시스템과 그 평가지표의 연구개발이 주요 사회문제로 대두되고 있다. 따라서 본 논문에서는 스마트 물 관리시스템의 자동화 수준 평가지표를 제안하고자 한다. 그 세부 연구내용은 다음과 같다. 첫째, 기존의 CMM과 SPICE 소프트웨어 프로세스 평가모델과 스마트공장의 평가지표를 검토하고, 스마트 정수처리장의 개념을 살펴본다. 둘째, 제안하는 스마트 물관리시스템의 평가지표에는 정수장의 주요 공정에 따라 착수 공정, 약품투입 공정, 혼화·응집 공정, 침전 공정, 여과 공정, 소독 공정의 6개 평가영역으로 세분화 하였고, 각 평가영역별로 0에서 4까지의 5단계 평가수준으로 구분하여 제안하였다.

• Journal of KIISE:Software and Applications
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• v.33 no.3
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• pp.267-276
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• 2006

IS 15504 and CMMI, etc are already proven models as a framework to improve the maturity of enterprise software development. However, these process maturity models can't present the detail and practical methods with which people can enhance the development competence and efficiency of an enterprise. Each company or organization should develop its own model or tailor the above models to make them suitable to its unique environment such as product or technology domain, scale of business or organization and cultural environment, etc for the practical application. This study introduces experiences that organizational and technical capability was reinforced based on our own process capability improvement model to improve software development strength in Samsung Electronics. We modeled our own improvement model which is expanded from IS 15504 against our experience. Our SPI model expanded its capability to organizational and technical issues including newly introduced capability level for evaluating its implementation. We expect that our study would give contribution for presenting industry experience and reference model for reinforcing software development competence.