• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.7 s.337
• /
• pp.35-40
• /
• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Economic and Environmental Geology
• /
• v.43 no.5
• /
• pp.429-441
• /
• 2010

The Sunrise Dam gold deposit is located approximately 850 km ENE of Perth, in the eastern part of the Yilgam Craton, Western Australia. The mine has produced approximately 153 t of Au at an average grade of 4.2 g/t, which stands for the most significant gold discoveries during the last decade in Western Australia. The deposit occurs in the Laverton Tectonic Zone corresponding to the corridor of structural complexity in the Laverton greenstone belt, and characterized by tight folding and thrusting. The mine stratigraphy consists of a complexly deformed and altered volcaniclastic and volcanic rocks. These have been overlain by a turbidite sequence containing generally well-sorted siltstones, sandstones and magnetite-rich shales, which are consistently fining upwards. These sequences have been intruded by quartz diorite, ultramafic dikes, and rhyodacite porphyry (Archean), and lamprophyre dikes (Palaeoproterozoic). These rocks constitute the asymmetric NNE-trending Spartan anticline with north-plunging thrust duplication of the BIF unit. The deposit is located on the western limb of this structure. Transported, fluvial-lacustrine and aeolean sediments lie unconformably over the deposit showing significant variation in relief. Gold mineralization occurs intermittently along a NE-trending corridor of ca. 4.5 km length. The 20 currently defined orebodies are centered on a series of parallel, gently-dipping ($\sim30^{\circ}$) and NESW trending shear zones with a thrust-duplex architecture and high-strain characteristics. The paragenetic sequence of the Sunrise Dam deposit can be divided into five hydrothermal stages ($D_1$, $D_2$, $D_3$, $D_4a$, $D_4b$), which are supported by distinctive features of the mineralogical assemblages. Among them, the D4a stage is the dominant episode of Au deposition, followed by the $D_4b$ stage, which is characterized by more diverse ore mineralogy including base metal sulfides, sulfosalts, and telluride minerals. The $D_4a$ stage contains higher proportions of microscopic free gold (48%) than D4b stage (12%), and pyrite is the principal host for native gold (electrum) followed by tetrahedrite-group minerals in both stages.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.7
• /
• pp.402-413
• /
• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.3
• /
• pp.62-70
• /
• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.901-908
• /
• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.25-32
• /
• 2020

In this paper, we propose an image generator for OLED panel test that can compensate for color coordinates and luminance by using panel defect inspection and optical measurement while displaying images on OLED panel. The proposed image generator consists of two processes: the image generation process and the process of compensating color coordinates and luminance using optical measurement. In the image generating process, the panel is set to receive the panel information to drive the panel, and the image is output by adjusting the output setting of the image generator according to the panel information. The output form of the image is configured by digital RGB method. The pattern generation algorithm inside the image generator outputs color and gray image data by transmitting color data to a 24-bit data line based on a synchronization signal according to the resolution of the panel. The process of compensating color coordinates and luminance using optical measurement outputs an image to an OLED panel in an image generator, and compensates for a portion where color coordinates and luminance data measured by an optical module differ from reference data. To evaluate the accuracy of the image generator for the OLED panel test proposed in this paper, Xilinx's Spartan 6 series XC6SLX25-FG484 FPGA was used and the design tool was ISE 14.5. The output of the image generation process was confirmed that the target setting value and the simulation result value for the digital RGB output using the oscilloscope matched. Compensating the color coordinates and luminance using optical measurements showed accuracy within the error rate suggested by the panel manufacturer.

• Journal of IKEEE
• /
• v.19 no.2
• /
• pp.168-175
• /
• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.9
• /
• pp.1803-1810
• /
• 2009

This paper designed IQ imbalance estimator and compensator to cancel the IQ imbalance error in DVB-T system using OFDM by Matlab. Among Matlab model, we designed and implemented IQ imbalance estimator and compensator by System Generator of Xilinx and Matlab model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model estimated and compensated IQ imbalance error very well. Also, we verified the performance through hardware co-simulation, timing analysis and resource estimation with Xilinx Spartan3 xc3s1000 fg676-4 target Device.

• Journal of Power Electronics
• /
• v.15 no.3
• /
• pp.670-684
• /
• 2015

The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys-2 Spartan-3E FPGA for a developed prototype.

• ETRI Journal
• /
• v.30 no.2
• /
• pp.227-237
• /
• 2008

In this paper, an algorithm that provides absolute and proportional differentiation of packet delays is proposed with the objective of enhancing quality of service in future packet networks. It features an adaptive scheme that adjusts the target delay for every time slot to compensate the deviation from the target delay, which is caused by prediction error on the traffic to arrive at the next time slot. It predicts the traffic to arrive at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized by the delay control operation for the next time slot to offset it. Because the proposed algorithm compensates the prediction error continuously, it shows superior adaptability to bursty traffic and exponential traffic. Through simulations we demonstrate that the algorithm meets the quantitative delay bounds and is robust to traffic fluctuation in comparison with the conventional non-adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA, and the performance is verified under the test board based on the XPC860P CPU.