• 제목/요약/키워드: SOG

검색결과 151건 처리시간 0.023초

SOI(Silicon-On-Insulator)- Micromachining 기술을 이용한 MEMS 소자의 제작 (Fabrication of MEMS Devices Using SOI(Silicon-On-Insulator)-Micromachining Technology)

  • 주병권;하주환;서상원;최승우;최우범
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.874-877
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    • 2001
  • SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

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고도 변형 무지외반증에서 새로운 Double Chevron 절골술 - 예비 보고 - (Double Chevron Osteotomy : New Surgical Technique for Severe Hallux Valgus - Preliminary Report -)

  • 류석우;윤준오;김유진;이기원;선명욱
    • 대한족부족관절학회지
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    • 제6권1호
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    • pp.96-99
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    • 2002
  • There are many reports on the various methods of treatment for hallux valgus. 1st metatarsal proximal osteotomy with distal soft tissue procedure or 1st metatarsophalangeal joint arthrodesis has been conventionally used for treatment of severe hallux valgus. We performed a new double chevron osteotomy in 3 cases and obtained satisfying results. We present this procedure as a new method of treatment for severe hallux valgus.

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Field Emission properties of photosensitive carbon nanotube paste with different inorganic binders

  • Park, Jae-Hong;Moon, Jin-San;Jeong, Jin-Soo;Yoo, Ji-Beom;Park, Chong-Yun;Nam, Joong- Woo;Park, Jong-Hwan;Choe, Deok-Hyeon
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.1451-1454
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    • 2005
  • We report effects of inorganic binder on the emission properties of CNT paste for low cost and high low-cost and large area field emission devices or displays. Two types of photosensitive carbon nanotube (CNT) paste were formulated by using of glass frit and spin on glass (SOG) as an inorganic binder and investigated their emission properties according to inorganic binders and firing conditions.

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Enhanced LTPS Manufacturing Equipment employing Excimer Laser Crystallization

  • Herbst, Ludolf;Simon, Frank;Rebhan, Ulrich;Geuking, Thorsten;Klaft, Ingo;Fechner, Burkhard
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.1123-1126
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    • 2005
  • For creation of low temperature polycrystallinesilicon (LTPS) the line beam excimer laser annealing (ELA) is a well known and established technique in mass production. With introduction of Sequential Lateral Solidification (SLS) some aspects such as crystalline quality, throughput and flexibility regarding the substrate size could be improved, but for OLED manufacturing still further process development is necessary. This paper discusses line beam ELA and SLS techniques that might enable process engineers to make polycrystalline-silicon (poly-Si) films with a high degree of uniformity and quality as required for system on glass (SOG) and active matrix organic light emitting displays (AMOLED). Equipment requirements are discussed and compared to previous standards. SEM images of process examples are shown in order to demonstrate the viability.

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Effect of electrical aging on emission stability of carbon nanotube paste

  • Park, J.H.;Moon, J.S.;Jeong, J.S.;Yoo, J.B.;Park, C.Y.;Moon, H.S.;Nam, J.W.;Kim, J.M.;Park, J.H.;Choe, D.H.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.1466-1469
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    • 2005
  • We report effects of electrical aging on the emission stability of carbon nanotube (CNT) paste for low cost and high low-cost and large area field emission devices or displays. Photosensitive carbon nanotube paste was formulated by using of spin on glass (SOG) as an inorganic binder and investigated emission properties and stability depending on electrical aging condition.

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그라핀 기판 제작 연구 (Research on Fabrication of Graphene Sheet)

  • 오세만;조원주;정종완
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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    • pp.384-384
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    • 2008
  • 그라핀 기판 제작을 위해서는 그라파이트의 탈착이 가장 핵심 기술이다. 본 연구에서는 신뢰성 있는 그라핀 기판 제작을 위해서, HOPG(Highly Ordered Pyrolytic Graphite) 기판에 고농도의 이온을 주입하고, HOPG를 이형기판에 본딩한후, 후속 열처리를 통해 HOPG를 탈착시켜 그리핀을 얻는 일련의 기본 실험에 대한 결과를 보여 주고자 한다. 기대하는 효과는 고농도의 수소/산소 이온의 경우 주입된 고농도의 수소/산소가 후속 열처리동안 이동 및 뭉침현상을 통해 HOPG기판 내에 수소압력(혹은 CO2 발생)을 증가시켜 HOPG를 자르는 것을 기대하고 있다. 일차 수소이온 주입의 실험결과, 기대와는 달리 $900^{\circ}C$ 열처리에도 절단현상이 발견되지 않아서 산소이온주입에 대한 추가실험을 진행 중이다. 그라핀 본딩의 경우 그라핀의 큰 roughness로 인해 $SiO_2$만의 Fusion 본딩은 불가능함을 여러 실험을 통해 알 수 있었고, 현재 SiO2/SOG 혹은 SiO2/Fox를 이용한 본딩실험을 진행중이다.

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효율적인 실시간 영상처리용 2-D 컨볼루션 필터 칩 (An Efficient 2-D Conveolver Chip for Real-Time Image Processing)

  • 은세영;선우명
    • 전자공학회논문지C
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    • 제34C권10호
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    • pp.1-7
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    • 1997
  • This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

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Template matching을 위한 새로운 알고리즘 및 ASIC 칩 구현 (A new template matching algorithm and its ASIC chip implementation)

  • 서승완;선우명훈
    • 전자공학회논문지C
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    • 제35C권1호
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    • pp.15-24
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    • 1998
  • This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

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한국 남해에서 출현한 옥돔과(Malacanthidae) 어류 1 미기록종 Hoplolatilus chlupatyi 치어의 형태기재 및 분자동정 (Morphological description and molecular identification of juvenile of the previously unrecorded species Hoplolatilus chlupatyi (Malacanthidae) in the South Sea of Korea)

  • 김이정;유효재;김진구
    • 수산해양기술연구
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    • 제56권4호
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    • pp.316-321
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    • 2020
  • A single juvenile malacanthid specimen (Hoplolatilus chlupatyi) was collected from the South Sea of Korea and identified by DNA barcoding. This species is readily distinguished from other malacanthid species in having well developed rostral spine and elongated spines in the posttemporal and preopercle. A molecular analysis based on mitochondrial DNA COI sequences showed that this species is matched to adult H. chlupatyi (genetic distance = 0.005). Therefore, this is the first record of H. chlupatyi in Korea. We propose new Korean names, "Mu-ji-gae-og-dom-sog" for the genus Hoplolatilus and "Mu-ji-gae-og-dom" for the species H. chlupatyi.

새로운 수리형태학 필터 VLSI 구조 설계 (Design of a new VLSI architecture for morphological filters)

  • 웅수환;선우명훈
    • 전자공학회논문지C
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    • 제34C권8호
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    • pp.22-38
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    • 1997
  • This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

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