• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of IKEEE
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• v.23 no.4
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• pp.1328-1336
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• 2019

To maintain the safe and optimal performance of batteries, accurate estimation of state of charge (SOC) is critical. In this paper, Long short-term memory network (LSTM) based on the artificial intelligence algorithm is applied to address the problem of the conventional coulomb-counting method. Different discharge cycles are concatenated to form the dataset for training and verification. In oder to improve the quality of input data for learning, preprocessing was performed. In addition, we compared learning ability and SOC estimation performance according to the structure of LSTM model and hyperparameter setup. The trained model was verified with a UDDS profile and achieved estimated accuracy of RMSE 0.82% and MAX 2.54%.

• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.6
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• pp.147-154
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• 2013

This study reports on the development and investigation of a BMS module using a new algorithm on the driving performance and battery life of electric vehicles. Here, the initial SOC was calculated using an open circuit voltage (OCV) method and a current integral method was later applied to the BMS module. We verified the performance of the BMS module by comparing both the results of the in-vehicle test and the BMS simulator test. Our verification test showed good agreement between the results of experiments and simulation with a small error of ${\pm}0.8%$. Here, we confirmed that the present, newly-developed BMS module not only can predict the battery life but can also monitor SOC, pack voltage, and current temperature.

• Proceedings of the KSRS Conference
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• v.1
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• pp.208-211
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• 2006

The contents of RF test set which can be used for checking the function and performance of 13m antenna installed in KARI site are described in this paper. For the purpose of considering RF test set as the transceiver in COMS, it is designed to retransmit the LRIT and HRIT in L-Band after receiving them in S-Band from 13m antenna. Additionally, this set has a function to turnaround raging tone used for the measurement of distance between satellite and 13m antenna. The required all equipments of RF test set are summarized with configuration. Measurements of several equipments which have already been delivered are described in this paper. The assembled RF test set will be used for the verification of 13m antenna

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.16-24
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• 2019

The performance of the battery management system (BMS) algorithm is important for ensuring the stability and efficient operation of battery packs. Such a performance is determined by the internal parameters of the electrical equivalent circuit model (EECM). This study proposes a performance improvement and verification of battery parameters for the BMS algorithm using electrical experiments and tools. The parameters were extracted through electrical characteristic experiments, and an EECM based on Ah counting was designed. Simulation results using the EECM were compared with actual experimental data to determine the best parameter extraction method.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.153-156
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• 2000

This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.305-313
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• 2012

We conducted thermal analyses and cooling tests of the space observation camera (SOC) of the multi-purpose infrared imaging system (MIRIS) to verify passive cooling. The thermal analyses were conducted with NX 7.0 TMG for two cases of attitude of the MIRIS: for the worst hot case and normal case. Through the thermal analyses of the flight model, it was found that even in the worst case the telescope could be cooled to less than $206^{\circ}K$. This is similar to the results of the passive cooling test (${\sim}200.2^{\circ}K$). For the normal attitude case of the analysis, on the other hand, the SOC telescope was cooled to about $160^{\circ}K$ in 10 days. Based on the results of these analyses and the test, it was determined that the telescope of the MIRIS SOC could be successfully cooled to below $200^{\circ}K$ with passive cooling. The SOC is, therefore, expected to have optimal performance under cooled conditions in orbit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.311-316
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• 2016

Batteries are critical components of electric vehicles and energy storage systems. The connection of a battery to the power grid for charge and discharge greatly affects energy storage. Therefore, an accurate and easy-to-observe battery model should be established to achieve systematic design, simulation, and SOC (state of charge) estimations. In this review, several equivalent circuit models of representative significance are explained, and their respective advantages and disadvantages are compared to determine and outline their reasonable applications to Li-ion batteries. Numerous commonly used model parameter identification principles are summarized as well, and basic model verification methods are briefly introduced for the convenient use of such models.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.56-61
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• 2000

Silicon semiconductor technology agrees that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduces verification time. This Paper describes the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.