• Clean Technology
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• v.10 no.2
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• pp.61-72
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• 2004

In this study, aqueous/semi-aqueous cleaning agents which consist of organic solvent, surfactant, cosurfactant, and water were developed by changing formulation parameters such as organic solvent type and contents, surfactant type and contents, and cosurfactant/surfactant(A/S) ratio, etc.. And physical properties and flux removal of the formulated cleaning agents have been evaluated. Also, the performance of oil-water separation from the rinse water contaminated during the cleaning process was evaluated for its recycling. The formulated cleaning agents in this work expected to have good penetration because of their low viscosity and low surface tension values of 30.2~32.5 dyne/cm. The flux removal with the terpene type cleaning agent was higher than that with hydrocarbon type cleaning agent and two commercial products (CPA(commercial product A), CPB(commercial product B)). And the performance of oil-water separation by gravity settling from the rinse water contaminated with formulated cleaning agent and soils was shown to be very good. The cleaning agents developed in this work were applied to surface mounting technology(SMT) cleaning process for manufacturing electronic parts at L electronic company. As a result, the newly developed cleaning agents showed two times better cleaning speed for removal of solder cream than the conventional ond containing ethanol and IPA(isopropyl alcohol). In addition, malodor and VOC problems generated by the previous organic cleaning agents have been solved in the manufacturing field through introduction of the non-volatile and environmental-friendly cleaning agents to the field.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.27-33
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• 2008

With increasing use of portable appliances such as PDA and cellular phone, changing environment of applications requires higher solder joint reliability. The ENIG (Electroless Nickel Immersion Gold) process has been widely used for fine pitch SMT (Surface Mount Technology) and BGA (Ball Grid Array) packaged devices due to its benefits including excellent solderability, high uniformity and substantial legibility throughout the packaging process. Its brittle fracture of solder, however, has received increasingly attentions. It was Down that fracture brittleness is mainly related with black pad resulting from galvanic nickel corrosion and P-enriched layer formation between the IMC (Intermetallic Compounds) and electroless nickel layer. Theoretically, smooth electroless Ni layer was blown to have a advantages in minimizing the black pad phenomenon by uniform solution exchange during immersion gold plating. Nevertheless, how to control the surface morphology of electroless Ni layer has been hardly blown. This study investigates an effect of surface morphology of Cu underlayer on surface morphology of electroless Ni layer. To obtain various kinds of surface morphology of Cu layer, two types of Cu etching chemical and a number of Cu etching treatment were applied.

• Annual Conference of KIPS
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• 2002.04b
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• pp.1619-1622
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• 2002

최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.481-486
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• 2010

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.3
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• pp.130-134
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• 2018

In the past few years, various solder compositions have been a representative material to electronic packages and surface mount technology industries as a replacement of Pb-base solder alloy. Therefore, extensive studies on process and/or reliability related with the low Ag composition have been reported because of recent rapid rise in Ag price. In this study, Sn-3.0Ag-0.5Cu, Sn-0.7Cu and Sn-0.3Ag-0.5Cu solder bar samples were fabricated by melting of Sn, Ag and Cu metal powders. Crystal structure and element concentration were analyzed by XRD, XRF, optical microscope, FE-SEM and EDS. The fabricated solder samples were composed of ${\beta}-Sn$, ${\varepsilon}-Ag_3Sn$ and ${\eta}-Cu_6Sn_5$ phases.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.80-80
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• 2009

패키징 구조의 발전이 점차 중요한 문제로 대두되어, 칩의 집적 기술의 발전에 따라 실장기술에서도 고속화, 소형화, 미세피치화, 고정밀화, 고밀도화가 요구되고있다. 최근 선진국을 중심으로 전자 전기기기 및 부품의 실장기술에서도 환경 친화적인 기술을 요구함에 따라, 저에너지 공정 및 무연 실장 기술에 대한 연구가 활발하게 진행되고 있다. 기존의 SOP(Small Out-line Package), QFP(Quad Flat Package) 등은 소형화, 다핀화, 고속화, 실장성에 한계가 있기 때문에, SMT(Surface Mount Technology) 형식으로 된 BGA(Ball Grid Array)가 휴대형 전화를 비롯한 기타 전자 부품 실장에 널리 사용되고 있다. BGA ball shear 법은 BGA 모듈의 생산 및 취급 중에 발생할지도 모르는 기판에 수평으로 작용하는 기계적인 전단력에 BGA solder ball이 견딜 수 있는 정도를 측정하기 위해 사용되는 시험법이다. 전단 시험에 의한 전단 강도의 측정 외에 전기전도도 측정, 파면 관찰, 이동거리(displacement), 유한요소 해석법 등을 병행하여 시험법의 신뢰성 향상에 대한 연구가 이루어지고 있다. 본 실험에서는 지름이 $500{\mu}m$인 Sn-3.5Ag 솔더볼을 이용하여 세라믹 기판을 접합하여 BGA 패키지를 완성하였다. 상부 기판에 솔더볼을 정렬시켜 리플로우 방법으로 접합 한 후 솔더볼이 접합된 상부 기판과 하부 기판을 접합 하여 시편을 제작하였다. 접합된 시편들은 $150^{\circ}C$에서 0~800시간 열처리를 실시하였고, 열처리를 하면서 각각 $3{\times}10^2A/cm^2,\;5{\times}10^3A/cm^2$의 전류를 인가하였다. 시편들을 전단 시험기를 이용하여 솔더볼의 기계적 특성 평가를 하였으며, 계면 반응을 관찰하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.