• The Korean Journal of Pharmacology
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• v.21 no.2
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• pp.79-89
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• 1985

Mechanism of calcium transport inhibition of cardiac sarcoplasmic reticulum (SR) by oxygen free radicals was examined. Effects of oxygen free radicals generated by xanthine/xanthine oxidase (X/XO) system on isolated porcine ventricle SR were studied with respect to its calcium binding, lipid peroxidation, SH-group content and alteration of membrane protein components. The results are as follows. 1) Calcium binding of isolated SR was markedly inhibited by X/XO. 2) During the incubation of sarcoplasmic reticulum with xanthine/xanthine oxidase, there were marked inclose in lipid peroxidation and reduction of SH-group content. 3) An antioxidant, p-phenylenediamine effectively prevented the lipid peroxidation but partially prevented the calcium binding inhibition of X/XO treated SR. 4) The reduction of SH-group content of SR treated with X/XO was partially prevented by p-phenylendiamine. 5) When modifying SH-group of SR by treatment with DTNB, the inhibition of calcium binding activity was partially prevented. 6) On gel-permeation chromatography of X/XO-treated sarcoplasmic reticulum, there was an increase of small molecular weight products, probably protein degradation products. 7) Semicarbazide, which prevents the cross-linking reaction of protein components, did not affect the calcium binding inhibition of X/XO-treated SR. From these results, it is suggested that the inhibition of calcium binding of SR by oxygen free radicals results from the consequence of multiple changes of SR components, which are lipid peroxidation, SH-group oxidation and degradation of protein components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.