• Review of KIISC
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• v.19 no.4
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• pp.44-52
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• 2009

2005년 중국의 Wang 교수 연구팀에 의해 SHA-1에 대한 충돌쌍 공격이 발표됨에 따라, SHA-1 대신 SHA-2를 사용하도록 하였다. 아직까지 SHA-2에는 SHA-1과 같은 문제점이 발생하지 않고 있지만, SHA-1과 설계 논리가 유사한 SHA-2에 문제점이 생겼을 경우 대체 알고리즘이 부재한 현 상황에 따라 SHA-3 알고리즘 개발의 필요성이 제기되었다. 이에 미국 국립기술 표준원 (NIST, National Institute of Standards and Technologies)는 신규 표준 해쉬 알고리즘을 개발을 위하여 2007년부터 2012년까지 6년간의 "SHA-3 프로젝트"를 시작하였다. 2008년 11월 1일 64개의 알고리즘이 제출되었으며, 12월 11일 51개의 알고리즘이 1 후보 알고리즘으로 선정되었다. 2009년 7월 현재, 10개의 알고리즘이 제안자에 의해 철회되어 41개의 알고리즘이 1 라운드에서 심사되고 있다. 본 논문에서는 SHA-3 개발의 요구 사항과 현재까지 SHA-3 개발 동얄을 서술한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Convergence Security Journal
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• v.16 no.7
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• pp.113-120
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• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.749-757
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• 2015

As the smart era, the use of smart devices is increasing. Smart devices are widely used to provide a human convenience, but there is a risk that information is exposed. The smart devices to prevent this problem includes the encryption algorithm. Among them, The hash function is an encryption algorithm that is used essentially to carry out the algorithm, such as data integrity, authentication, signature. As the issue raised in the collision resistance of SHA-1 has recently been causing a safety problem, and SHA-1 hash function based on the current standard of SHA-2 would also be a problem in the near future safety. Accordingly, NIST selected KECCAK algorithm as SHA-3, it has become necessary to implement this in various environments for this algorithm. In this paper, implementation of KECCAK algorithm. And SHA-2 On The ARM-11 processor, and compare performance.

• Journal of Acupuncture Research
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• v.22 no.3
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• pp.53-67
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• 2005

Objective : The purpose of this study is to observe the effects of Scolopendrid Aqua-acupuncture applied to the L14 on galactosamine-induced liver injury in rats. Methods : In this study, the experimental rats were divided four groups(Control group, SHA-1, SHA-2, SHA-3 group). In the Control group, we first injected galactosamine and then didn`t treated. In the SHA-1, SHA-2, SHA~3 group, we first Injected galactosamine and then injected Scolopendrid aqua-acupuncture applied to L14, each 0.083mg/kg, 0.017 mg/kg, 0.008mg/kg. We observed the changes of GOT, GPT, ${\gamma}$-GTP, Total bilirubin, LDH, ALP, Total cholesterol, Triglyceride, HDL-cholesterol, WBC, RBC, HGB, Hct. Results & Conclusion: 1. In the change of GPT content, as compared with control group, SHA-2, SHA-3 groups were significantly decreased. 2. In the change of ${\gamma}$-GTP content, as compared with control group, SHA-1, SHA-2 groups were significantly decreased. 3. In the change of Total bilirubin content, as compared with control group, SHA-2 group was significantly decreased.

• Physical Therapy Korea
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• v.25 no.1
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• pp.22-30
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• 2018

Background: Improvement of lumbo-pelvic stability can reduce the compensatory action of the quadratus lumborum (QL) and selectively strengthen the gluteus medius (GM) during side-lying hip abduction (SHA). There are abdominal draw-in maneuver (ADIM) and abdominal bracing (AB) as active ways, and pelvic compression belt (PCB) as a passive way to increase of lumbo-pelvic stability. It is necessary to compare how these stabilization methods affect the selective strengthening of the GM. Objects: To investigate the effects of ADIM, AB, and PCB during SHA on the electromyography (EMG) activity of the GM, QL, external oblique (EO) and internal oblique (IO), and the GM/QL EMG activity ratio. Methods: A total of 20 healthy male adults participated in the study. The subjects performed three conditions in side-lying in random order: SHA with ADIM (SHA-ADIM), SHA with AB (SHA-AB), and SHA with PCB (SHA-PCB). To compare the differences among the three conditions, the EMG activities of the GM, QL, EO and IO, and GM/QL EMG activity ratio were analyzed using one-way repeated ANOVA. Results: The EMG activity of the QL was significantly higher in SHA-AB than in SHA-ADIM and SHA-PCB. The GM/QL activity ratio was significantly higher in SHA-PCB than in SHA-ADIM and SHA-AB. In addition, the figure for SHA-ADIM was significantly higher than that for SHA-AB. In the case of the EO, the figure for SHA-AB was significantly higher than corresponding values for the other two conditions. The figure for SHA-ADIM was significantly higher than that for SHA-PCB. The EMG activity of the IO was significantly higher in SHA-AH than in SHA-PCB. Conclusion: It can be suggested that wearing the PCB can more selectively strengthen the GM than to perform ADIM and AB during SHA. In addition, the ADIM can be recommended when there is a need to strengthen abdominal muscles during SHA.

• Review of KIISC
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• v.16 no.4
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• pp.25-33
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• 2006

중국의 Wang 교수 등은 2004년부터 차분 공격을 이용하여 대표적인 해쉬함수인 MD4, MD5, RIPEMD, HAVAL, SHA-0에 대한 충돌쌍을 찾았다. 그들은 아직까지 SHA-1에 대한 충돌쌍을 찾지는 못했지만 생일 공격보다 빠른 방법으로 SHA-1의 충돌쌍을 찾을 수 있음을 이론적으로 보였으며 58단계 SHA-1(SHA-1의 전체는 80단계)에 대해서는 구체적인 충돌쌍을 찾았다. 본 논문에서는 Wang 교수 등이 개발한 차분 공격법에 대해서 살펴보기로 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.115-125
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• 2011

Cryptographic hash functions are also called one-way functions and they ensure the integrity of communication data and command by detecting or blocking forgery. Also hash functions can be used with other security protocols for signature, authentication, and key distribution. The SHA-1 was widely used until it was found to be cryptographically broken by Wang, et. al, 2005. For this reason, NIST launched the SHA-3 competition in November 2007 to develop new secure hash function by 2012. Many SHA-3 hash functions were proposed and currently in review process. To choose new SHA-3 hash function among the proposed hash functions, there have been many efforts to analyze the cryptographic secureness, hardware/software characteristics on each proposed one. However there are few research efforts on the SHA-3 from the point of power consumption, which is a crucial metric on hardware module. In this paper, we analyze the power consumption characteristics of the SHA-3 hash functions when they are made in the form of ASIC hardware module. Also we propose power efficient hardware architecture on Luffa, which is strong candidate as a new SHA-3 hash function. Our proposed low power architecture for Luffa achieves 10% less power consumption than previous Luffa hardware architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.