• Title/Summary/Keyword: SD-generated

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The Design and Evaluation of BACF/DCF for Mobile OIS Gyro Sensor's Zero Point angle Following (모바일 OIS(Optical Image Stabilization) 자이로 센서의 영점 각도 추종을 위한 BACF/DCF 설계 및 평가)

  • Lee, Seung-Kwon;Kong, Jin-Heung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.8
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    • pp.16-21
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    • 2012
  • The gyro sensor that made by MEMS process is generated an accumulated error(drift) and escape the zero angle following during calculation of rotate angle. This study propose BACF(Boot Angle Compensation Filter) algorithm for prevent escape zero angle and DCF algorithm for remove accumulated error. DCF algorithm is designed for acquire accurate turn of ratio by remove offset and noise components. BACF algorithm is obtained average offset that removed noise components by recursively calculate. Experimental environment, two-axis gyro sensor and mobile OIS camera mounted control board and 5Hz oscillation of ${\pm}0.5^{\circ}$ for the experiments were carried out. BACF and DCF algorithm is applied and the resulting accumulated error did not occur and exactly zero angle following results were made.

A Real-time SoC Design of Foreground Object Segmentation (Foreground 객체 추출을 위한 실시간 SoC 설계)

  • Kim Ji-Su;Lee Tae-Ho;Lee Hyuk-Jae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.44-52
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    • 2006
  • Recently developed MPEG-4 Part 2 compression standard provides a novel capability to handle arbitrary video objects. To support this capability, an efficient object segmentation technique is required. This paper proposes a real-time algorithm for foreground object segmentation in video sequences. The proposed algorithm consists of two steps: the first step that segments a video frame into multiple sub-regions using Spatio-Temporal Watershed Transform and the second step in which a foreground object segment is extracted from the sub-regions generated in the first step. For real-time processing, the algorithm is partitioned into hardware and software parts so that computationally expensive parts are off-loaded from a processor and executed by hardware accelerators. Simulation results show that the proposed implementation can handle QCIF-size video at 15 fps and extracts an accurate foreground object.

Automatic generation of higher level design diagrams (상위 수준 설계 도면의 자동 생성)

  • Lee, Eun-Choul;Kim, Kyo-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.23-32
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    • 2005
  • The automatic generation of circuit diagrams has been practically used in the HDL based design for decades. Nevertheless, the diagrams became too complicated for the designers to identify the signal flows in the RTL and system level designs. In this paper, we propose four techniques to enhance the roadability of the complicated diagrams. They include i) the transformation of repetitive instances and terminals into vector forms, ii) an improved loop breaking algorithm, iii) a flat tap which simplifies the two level bus ripping structure that is required for the connection of a bundle net to multiple buses, and iv) the identification of block strings, and alignment of the corresponding blocks. Towards validating the proposed techniques, the diagrams of an industrial strength design m generated. The complexity of the diagrams has been reduced by up to $90\%$ in terms of the number of wires, the aggregate wire length, and the area.

Efficient Global Placement Using Hierarchical Partitioning Technique and Relaxation Based Local Search (계층적 분할 기법과 완화된 국부 탐색 알고리즘을 이용한 효율적인 광역 배치)

  • Sung Young-Tae;Hur Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.61-70
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    • 2005
  • In this paper, we propose an efficient global placement algorithm which is an enhanced version of Hybrid Placer$^{[25]}$, a standard cell placement tool, which uses a middle-down approach. Combining techniques used in the well-known partitioner hMETIS and the RBLS(Relaxation Based Local Search) in Hybrid Placer improves the quality of global placements. Partitioning techniques of hMETIS is applied in a top-down manner and RBLS is used in each level of the top-down hierarchy to improve the global placement. The proposed new approach resolves the problem that Hybrid Placer seriously depends on initial placements and it speeds up without deteriorating the placement quality. Experimental results prove that solutions generated by the proposed method on the MCNC benchmarks are comparable to those by FengShui which is a well known placement tool. Compared to the results of the original Hybrid Placer, new method is 5 times faster on average and shows improvement on bigger circuits.

An Accurate Current Reference using Temperature and Process Compensation Current Mirror (온도 및 공정 보상 전류 미러를 이용한 정밀한 전류 레퍼런스)

  • Yang, Byung-Do
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.79-85
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    • 2009
  • In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. However, the temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT current is measured, the switch codes of the TPC-CM is fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation for $20^{\circ}$C${\sim}$100$^{\circ}$C.

Analysis of Split Power/Ground Plane Structures for Radiated EMI Reduction (EMI 저감을 위해 분할된 전원/접지 평판 구조에서의 방사성 방출 분석)

  • Lee, Jang-Hoon;Lee, Pil-Soo;Lee, Tae-Heon;Kim, Chang-Gyun;Song, In-Chae;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.6
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    • pp.43-50
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    • 2010
  • In this paper, we analyzed radiated emission generated by the split power/ground plane structures in order to reduce EMI in system modules. The magnetic fields and electric fields were simulated and measured on the test boards under various conditions. In order to reduce radiated emission, we have to determine spacing and location of the split ground gap so that input signal frequency does not coincide with the resonance frequency of the split power/ground plane structure and the phase of reflection coefficient is close to $0^{\circ}$ at input signal frequency. Moreover, we found that inserting a stitching capacitor could reduce the radiated emission. Low magnitude of reflection coefficient and the phase close to $0^{\circ}$ are required to reduce radiated emission. It is necessary to properly decide value and location of a stitching capacitor to fulfil those requirements.

Clocked Low Power Rail-to-Rail Sense Amplifier for Ternary Content Addressable Memory (TCAM) Application (Ternary Content Addressable Memory를 위한 저 전력 Rail-to-Rail 감지 증폭기)

  • Ahn, Sang-Wook;Jung, Chang-Min;Lim, Chul-Seung;Lee, Soon-Young;Baeg, Sang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.2
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    • pp.39-46
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    • 2012
  • The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

Monte Carlo Based Planning System for a Beam Spoiler

  • 강세권;조병철;박희철;배훈식
    • Proceedings of the Korean Society of Medical Physics Conference
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    • 2003.09a
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    • pp.56-56
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    • 2003
  • For the treatment of superficial tumors like squamous cell carcinoma of the head and neck, 6 MV photon beam is not appropriate and a spoiler is widely used to increase dose in the buildup region, while preserving the skin sparing effect. However, commercially available treatment planning systems assume a normal unspoiled beam, thereby cannot predict the buildup dose with spoiler accurately. We aimed to implement a Monte Carlo (MC) based planning system to apply it to the radiation treatment of head and neck. Lucite with thickness of 10-mm was used for the beam spoiler with Siemens Primus 6 MV photon beam. BEAM/DOSXYZ MC system was employed to model the linac and the spoiler. To verify the calculation accuracy of MC simulations, the percent depth doses (PDDs) and profiles with and without spoiler were measured using a parallel-plate chamber. For the MC based planning, we adopted a hybrid interface system between Pinnacle (Philips, USA) and BEAM/DOSXYZ to support treatment parameters of Siemens linac and the spoiler. The measurements of PDDs and profiles agreed with the corresponding MC simulations within 2% (lSD), which demonstrate the reliability of our MC simulations. The spoiler generated electrons make a contribution to the absorbed dose up to depth of 2cm, which shows that the dominant source of increased dose from spoiler system is the contaminating electrons created by the spoiler. The whole procedures necessary for MC based treatment planning were performed seamlessly between Pinnacle and BEAM/DOSXYZ system. This ability helps to increase the clinical efficiency of the spoiler technique. In conclusion, we implemented a MC based treatment planning system for a 6 MV photon beam with a spoiler. We demonstrate sophisticated MC technique makes it possible to predict dose distributions around buildup region accurately.

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A Study on Logic Built-In Self-Test Using Modified Pseudo-random Patterns (수정된 의사 무작위 패턴을 이용한 효율적인 로직 내장 자체 테스트에 관한 연구)

  • Lee Jeong-Min;Chang Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.8 s.350
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    • pp.27-34
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    • 2006
  • During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

Design of a CMOS RFID Transponder IC Using a New Damping Circuit (새로운 감폭회로를 사용한 CMOS RFID 트랜스폰더 IC 설계)

  • O, Won-Seok;Lee, Sang-Hun;Lee, Gang-Myeong;Park, Jong-Tae;Yu, Jong-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.3
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    • pp.211-219
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    • 2001
  • This paper describes a read-only CMOS transponder IC for RFID applications. A full-wave rectifier implemented using NMOS transistors supplies the transponder with a dc supply voltage using the magnetic field generated from a reader. A 64-bit ROM has been designed for a data memory. Front-end impedance modulation and Manchester coding are used for transmitting the data from the transponder memory to the reader. A new damping circuit which has almost constant damping rate under the variations of the distance between the transponder and the reader has been employed for impedance modulation. The designed circuit has been fabricated using a 0.65${\mu}{\textrm}{m}$2-poly, 2-metal CMOS process. Die area is 0.9mm$\times$0.4mm. Measurement results show that it has a constant damping rate of around 20~25% and a data transmission rate of 3.9kbps at a 125KHz RF carrier. The power required for reading operation is about 100㎼. The measured reading distance is around 7cm.

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